1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Register `INT_RAW` writer"]
4pub type W = crate::W<INT_RAW_SPEC>;
5#[doc = "Field `TIMER0_STOP` reader - The raw status bit for the interrupt triggered when the timer 0 stops."]
6pub type TIMER0_STOP_R = crate::BitReader;
7#[doc = "Field `TIMER0_STOP` writer - The raw status bit for the interrupt triggered when the timer 0 stops."]
8pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TIMER1_STOP` reader - The raw status bit for the interrupt triggered when the timer 1 stops."]
10pub type TIMER1_STOP_R = crate::BitReader;
11#[doc = "Field `TIMER1_STOP` writer - The raw status bit for the interrupt triggered when the timer 1 stops."]
12pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TIMER2_STOP` reader - The raw status bit for the interrupt triggered when the timer 2 stops."]
14pub type TIMER2_STOP_R = crate::BitReader;
15#[doc = "Field `TIMER2_STOP` writer - The raw status bit for the interrupt triggered when the timer 2 stops."]
16pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TIMER0_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
18pub type TIMER0_TEZ_R = crate::BitReader;
19#[doc = "Field `TIMER0_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
20pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TIMER1_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
22pub type TIMER1_TEZ_R = crate::BitReader;
23#[doc = "Field `TIMER1_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
24pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TIMER2_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
26pub type TIMER2_TEZ_R = crate::BitReader;
27#[doc = "Field `TIMER2_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
28pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TIMER0_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
30pub type TIMER0_TEP_R = crate::BitReader;
31#[doc = "Field `TIMER0_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
32pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TIMER1_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
34pub type TIMER1_TEP_R = crate::BitReader;
35#[doc = "Field `TIMER1_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
36pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TIMER2_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
38pub type TIMER2_TEP_R = crate::BitReader;
39#[doc = "Field `TIMER2_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
40pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FAULT0` reader - The raw status bit for the interrupt triggered when event_f0 starts."]
42pub type FAULT0_R = crate::BitReader;
43#[doc = "Field `FAULT0` writer - The raw status bit for the interrupt triggered when event_f0 starts."]
44pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FAULT1` reader - The raw status bit for the interrupt triggered when event_f1 starts."]
46pub type FAULT1_R = crate::BitReader;
47#[doc = "Field `FAULT1` writer - The raw status bit for the interrupt triggered when event_f1 starts."]
48pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `FAULT2` reader - The raw status bit for the interrupt triggered when event_f2 starts."]
50pub type FAULT2_R = crate::BitReader;
51#[doc = "Field `FAULT2` writer - The raw status bit for the interrupt triggered when event_f2 starts."]
52pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `FAULT0_CLR` reader - The raw status bit for the interrupt triggered when event_f0 ends."]
54pub type FAULT0_CLR_R = crate::BitReader;
55#[doc = "Field `FAULT0_CLR` writer - The raw status bit for the interrupt triggered when event_f0 ends."]
56pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `FAULT1_CLR` reader - The raw status bit for the interrupt triggered when event_f1 ends."]
58pub type FAULT1_CLR_R = crate::BitReader;
59#[doc = "Field `FAULT1_CLR` writer - The raw status bit for the interrupt triggered when event_f1 ends."]
60pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `FAULT2_CLR` reader - The raw status bit for the interrupt triggered when event_f2 ends."]
62pub type FAULT2_CLR_R = crate::BitReader;
63#[doc = "Field `FAULT2_CLR` writer - The raw status bit for the interrupt triggered when event_f2 ends."]
64pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `CMPR0_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
66pub type CMPR0_TEA_R = crate::BitReader;
67#[doc = "Field `CMPR0_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
68pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `CMPR1_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
70pub type CMPR1_TEA_R = crate::BitReader;
71#[doc = "Field `CMPR1_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
72pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `CMPR2_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
74pub type CMPR2_TEA_R = crate::BitReader;
75#[doc = "Field `CMPR2_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
76pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `CMPR0_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
78pub type CMPR0_TEB_R = crate::BitReader;
79#[doc = "Field `CMPR0_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
80pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `CMPR1_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
82pub type CMPR1_TEB_R = crate::BitReader;
83#[doc = "Field `CMPR1_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
84pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `CMPR2_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
86pub type CMPR2_TEB_R = crate::BitReader;
87#[doc = "Field `CMPR2_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
88pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `TZ0_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
90pub type TZ0_CBC_R = crate::BitReader;
91#[doc = "Field `TZ0_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
92pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `TZ1_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
94pub type TZ1_CBC_R = crate::BitReader;
95#[doc = "Field `TZ1_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
96pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `TZ2_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
98pub type TZ2_CBC_R = crate::BitReader;
99#[doc = "Field `TZ2_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
100pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `TZ0_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
102pub type TZ0_OST_R = crate::BitReader;
103#[doc = "Field `TZ0_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
104pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `TZ1_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
106pub type TZ1_OST_R = crate::BitReader;
107#[doc = "Field `TZ1_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
108pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `TZ2_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
110pub type TZ2_OST_R = crate::BitReader;
111#[doc = "Field `TZ2_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
112pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `CAP0` reader - The raw status bit for the interrupt triggered by capture on channel 0."]
114pub type CAP0_R = crate::BitReader;
115#[doc = "Field `CAP0` writer - The raw status bit for the interrupt triggered by capture on channel 0."]
116pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
117#[doc = "Field `CAP1` reader - The raw status bit for the interrupt triggered by capture on channel 1."]
118pub type CAP1_R = crate::BitReader;
119#[doc = "Field `CAP1` writer - The raw status bit for the interrupt triggered by capture on channel 1."]
120pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
121#[doc = "Field `CAP2` reader - The raw status bit for the interrupt triggered by capture on channel 2."]
122pub type CAP2_R = crate::BitReader;
123#[doc = "Field `CAP2` writer - The raw status bit for the interrupt triggered by capture on channel 2."]
124pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
125impl R {
126 #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
127 #[inline(always)]
128 pub fn timer0_stop(&self) -> TIMER0_STOP_R {
129 TIMER0_STOP_R::new((self.bits & 1) != 0)
130 }
131 #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
132 #[inline(always)]
133 pub fn timer1_stop(&self) -> TIMER1_STOP_R {
134 TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
135 }
136 #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
137 #[inline(always)]
138 pub fn timer2_stop(&self) -> TIMER2_STOP_R {
139 TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
140 }
141 #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
142 #[inline(always)]
143 pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
144 TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
145 }
146 #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
147 #[inline(always)]
148 pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
149 TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
150 }
151 #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
152 #[inline(always)]
153 pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
154 TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
155 }
156 #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
157 #[inline(always)]
158 pub fn timer0_tep(&self) -> TIMER0_TEP_R {
159 TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
160 }
161 #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
162 #[inline(always)]
163 pub fn timer1_tep(&self) -> TIMER1_TEP_R {
164 TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
165 }
166 #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
167 #[inline(always)]
168 pub fn timer2_tep(&self) -> TIMER2_TEP_R {
169 TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
170 }
171 #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
172 #[inline(always)]
173 pub fn fault0(&self) -> FAULT0_R {
174 FAULT0_R::new(((self.bits >> 9) & 1) != 0)
175 }
176 #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
177 #[inline(always)]
178 pub fn fault1(&self) -> FAULT1_R {
179 FAULT1_R::new(((self.bits >> 10) & 1) != 0)
180 }
181 #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
182 #[inline(always)]
183 pub fn fault2(&self) -> FAULT2_R {
184 FAULT2_R::new(((self.bits >> 11) & 1) != 0)
185 }
186 #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
187 #[inline(always)]
188 pub fn fault0_clr(&self) -> FAULT0_CLR_R {
189 FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
190 }
191 #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
192 #[inline(always)]
193 pub fn fault1_clr(&self) -> FAULT1_CLR_R {
194 FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
195 }
196 #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
197 #[inline(always)]
198 pub fn fault2_clr(&self) -> FAULT2_CLR_R {
199 FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
200 }
201 #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
202 #[inline(always)]
203 pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
204 CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
205 }
206 #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
207 #[inline(always)]
208 pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
209 CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
210 }
211 #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
212 #[inline(always)]
213 pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
214 CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
215 }
216 #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
217 #[inline(always)]
218 pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
219 CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
220 }
221 #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
222 #[inline(always)]
223 pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
224 CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
225 }
226 #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
227 #[inline(always)]
228 pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
229 CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
230 }
231 #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
232 #[inline(always)]
233 pub fn tz0_cbc(&self) -> TZ0_CBC_R {
234 TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
235 }
236 #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
237 #[inline(always)]
238 pub fn tz1_cbc(&self) -> TZ1_CBC_R {
239 TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
240 }
241 #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
242 #[inline(always)]
243 pub fn tz2_cbc(&self) -> TZ2_CBC_R {
244 TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
245 }
246 #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
247 #[inline(always)]
248 pub fn tz0_ost(&self) -> TZ0_OST_R {
249 TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
250 }
251 #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
252 #[inline(always)]
253 pub fn tz1_ost(&self) -> TZ1_OST_R {
254 TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
255 }
256 #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
257 #[inline(always)]
258 pub fn tz2_ost(&self) -> TZ2_OST_R {
259 TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
260 }
261 #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
262 #[inline(always)]
263 pub fn cap0(&self) -> CAP0_R {
264 CAP0_R::new(((self.bits >> 27) & 1) != 0)
265 }
266 #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
267 #[inline(always)]
268 pub fn cap1(&self) -> CAP1_R {
269 CAP1_R::new(((self.bits >> 28) & 1) != 0)
270 }
271 #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
272 #[inline(always)]
273 pub fn cap2(&self) -> CAP2_R {
274 CAP2_R::new(((self.bits >> 29) & 1) != 0)
275 }
276}
277#[cfg(feature = "impl-register-debug")]
278impl core::fmt::Debug for R {
279 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
280 f.debug_struct("INT_RAW")
281 .field("timer0_stop", &self.timer0_stop())
282 .field("timer1_stop", &self.timer1_stop())
283 .field("timer2_stop", &self.timer2_stop())
284 .field("timer0_tez", &self.timer0_tez())
285 .field("timer1_tez", &self.timer1_tez())
286 .field("timer2_tez", &self.timer2_tez())
287 .field("timer0_tep", &self.timer0_tep())
288 .field("timer1_tep", &self.timer1_tep())
289 .field("timer2_tep", &self.timer2_tep())
290 .field("fault0", &self.fault0())
291 .field("fault1", &self.fault1())
292 .field("fault2", &self.fault2())
293 .field("fault0_clr", &self.fault0_clr())
294 .field("fault1_clr", &self.fault1_clr())
295 .field("fault2_clr", &self.fault2_clr())
296 .field("cmpr0_tea", &self.cmpr0_tea())
297 .field("cmpr1_tea", &self.cmpr1_tea())
298 .field("cmpr2_tea", &self.cmpr2_tea())
299 .field("cmpr0_teb", &self.cmpr0_teb())
300 .field("cmpr1_teb", &self.cmpr1_teb())
301 .field("cmpr2_teb", &self.cmpr2_teb())
302 .field("tz0_cbc", &self.tz0_cbc())
303 .field("tz1_cbc", &self.tz1_cbc())
304 .field("tz2_cbc", &self.tz2_cbc())
305 .field("tz0_ost", &self.tz0_ost())
306 .field("tz1_ost", &self.tz1_ost())
307 .field("tz2_ost", &self.tz2_ost())
308 .field("cap0", &self.cap0())
309 .field("cap1", &self.cap1())
310 .field("cap2", &self.cap2())
311 .finish()
312 }
313}
314impl W {
315 #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
316 #[inline(always)]
317 pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_RAW_SPEC> {
318 TIMER0_STOP_W::new(self, 0)
319 }
320 #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
321 #[inline(always)]
322 pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_RAW_SPEC> {
323 TIMER1_STOP_W::new(self, 1)
324 }
325 #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
326 #[inline(always)]
327 pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_RAW_SPEC> {
328 TIMER2_STOP_W::new(self, 2)
329 }
330 #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
331 #[inline(always)]
332 pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_RAW_SPEC> {
333 TIMER0_TEZ_W::new(self, 3)
334 }
335 #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
336 #[inline(always)]
337 pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_RAW_SPEC> {
338 TIMER1_TEZ_W::new(self, 4)
339 }
340 #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
341 #[inline(always)]
342 pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_RAW_SPEC> {
343 TIMER2_TEZ_W::new(self, 5)
344 }
345 #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
346 #[inline(always)]
347 pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_RAW_SPEC> {
348 TIMER0_TEP_W::new(self, 6)
349 }
350 #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
351 #[inline(always)]
352 pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_RAW_SPEC> {
353 TIMER1_TEP_W::new(self, 7)
354 }
355 #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
356 #[inline(always)]
357 pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_RAW_SPEC> {
358 TIMER2_TEP_W::new(self, 8)
359 }
360 #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
361 #[inline(always)]
362 pub fn fault0(&mut self) -> FAULT0_W<INT_RAW_SPEC> {
363 FAULT0_W::new(self, 9)
364 }
365 #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
366 #[inline(always)]
367 pub fn fault1(&mut self) -> FAULT1_W<INT_RAW_SPEC> {
368 FAULT1_W::new(self, 10)
369 }
370 #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
371 #[inline(always)]
372 pub fn fault2(&mut self) -> FAULT2_W<INT_RAW_SPEC> {
373 FAULT2_W::new(self, 11)
374 }
375 #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
376 #[inline(always)]
377 pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_RAW_SPEC> {
378 FAULT0_CLR_W::new(self, 12)
379 }
380 #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
381 #[inline(always)]
382 pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_RAW_SPEC> {
383 FAULT1_CLR_W::new(self, 13)
384 }
385 #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
386 #[inline(always)]
387 pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_RAW_SPEC> {
388 FAULT2_CLR_W::new(self, 14)
389 }
390 #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
391 #[inline(always)]
392 pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<INT_RAW_SPEC> {
393 CMPR0_TEA_W::new(self, 15)
394 }
395 #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
396 #[inline(always)]
397 pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<INT_RAW_SPEC> {
398 CMPR1_TEA_W::new(self, 16)
399 }
400 #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
401 #[inline(always)]
402 pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<INT_RAW_SPEC> {
403 CMPR2_TEA_W::new(self, 17)
404 }
405 #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
406 #[inline(always)]
407 pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<INT_RAW_SPEC> {
408 CMPR0_TEB_W::new(self, 18)
409 }
410 #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
411 #[inline(always)]
412 pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<INT_RAW_SPEC> {
413 CMPR1_TEB_W::new(self, 19)
414 }
415 #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
416 #[inline(always)]
417 pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<INT_RAW_SPEC> {
418 CMPR2_TEB_W::new(self, 20)
419 }
420 #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
421 #[inline(always)]
422 pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<INT_RAW_SPEC> {
423 TZ0_CBC_W::new(self, 21)
424 }
425 #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
426 #[inline(always)]
427 pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<INT_RAW_SPEC> {
428 TZ1_CBC_W::new(self, 22)
429 }
430 #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
431 #[inline(always)]
432 pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<INT_RAW_SPEC> {
433 TZ2_CBC_W::new(self, 23)
434 }
435 #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
436 #[inline(always)]
437 pub fn tz0_ost(&mut self) -> TZ0_OST_W<INT_RAW_SPEC> {
438 TZ0_OST_W::new(self, 24)
439 }
440 #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
441 #[inline(always)]
442 pub fn tz1_ost(&mut self) -> TZ1_OST_W<INT_RAW_SPEC> {
443 TZ1_OST_W::new(self, 25)
444 }
445 #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
446 #[inline(always)]
447 pub fn tz2_ost(&mut self) -> TZ2_OST_W<INT_RAW_SPEC> {
448 TZ2_OST_W::new(self, 26)
449 }
450 #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
451 #[inline(always)]
452 pub fn cap0(&mut self) -> CAP0_W<INT_RAW_SPEC> {
453 CAP0_W::new(self, 27)
454 }
455 #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
456 #[inline(always)]
457 pub fn cap1(&mut self) -> CAP1_W<INT_RAW_SPEC> {
458 CAP1_W::new(self, 28)
459 }
460 #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
461 #[inline(always)]
462 pub fn cap2(&mut self) -> CAP2_W<INT_RAW_SPEC> {
463 CAP2_W::new(self, 29)
464 }
465}
466#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
467pub struct INT_RAW_SPEC;
468impl crate::RegisterSpec for INT_RAW_SPEC {
469 type Ux = u32;
470}
471#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
472impl crate::Readable for INT_RAW_SPEC {}
473#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
474impl crate::Writable for INT_RAW_SPEC {
475 type Safety = crate::Unsafe;
476 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
477 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
478}
479#[doc = "`reset()` method sets INT_RAW to value 0"]
480impl crate::Resettable for INT_RAW_SPEC {
481 const RESET_VALUE: u32 = 0;
482}