1#[doc = "Register `USER` reader"]
2pub type R = crate::R<USER_SPEC>;
3#[doc = "Register `USER` writer"]
4pub type W = crate::W<USER_SPEC>;
5#[doc = "Field `DOUTDIN` reader - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
6pub type DOUTDIN_R = crate::BitReader;
7#[doc = "Field `DOUTDIN` writer - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
8pub type DOUTDIN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `QPI_MODE` reader - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
10pub type QPI_MODE_R = crate::BitReader;
11#[doc = "Field `QPI_MODE` writer - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
12pub type QPI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OPI_MODE` reader - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."]
14pub type OPI_MODE_R = crate::BitReader;
15#[doc = "Field `OPI_MODE` writer - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."]
16pub type OPI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
18pub type TSCK_I_EDGE_R = crate::BitReader;
19#[doc = "Field `TSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
20pub type TSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CS_HOLD` reader - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
22pub type CS_HOLD_R = crate::BitReader;
23#[doc = "Field `CS_HOLD` writer - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
24pub type CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CS_SETUP` reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
26pub type CS_SETUP_R = crate::BitReader;
27#[doc = "Field `CS_SETUP` writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
28pub type CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
30pub type RSCK_I_EDGE_R = crate::BitReader;
31#[doc = "Field `RSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
32pub type RSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CK_OUT_EDGE` reader - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
34pub type CK_OUT_EDGE_R = crate::BitReader;
35#[doc = "Field `CK_OUT_EDGE` writer - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
36pub type CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FWRITE_DUAL` reader - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
38pub type FWRITE_DUAL_R = crate::BitReader;
39#[doc = "Field `FWRITE_DUAL` writer - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
40pub type FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FWRITE_QUAD` reader - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
42pub type FWRITE_QUAD_R = crate::BitReader;
43#[doc = "Field `FWRITE_QUAD` writer - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
44pub type FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FWRITE_OCT` reader - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."]
46pub type FWRITE_OCT_R = crate::BitReader;
47#[doc = "Field `FWRITE_OCT` writer - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."]
48pub type FWRITE_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `USR_CONF_NXT` reader - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
50pub type USR_CONF_NXT_R = crate::BitReader;
51#[doc = "Field `USR_CONF_NXT` writer - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
52pub type USR_CONF_NXT_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `SIO` reader - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
54pub type SIO_R = crate::BitReader;
55#[doc = "Field `SIO` writer - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
56pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `USR_MISO_HIGHPART` reader - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
58pub type USR_MISO_HIGHPART_R = crate::BitReader;
59#[doc = "Field `USR_MISO_HIGHPART` writer - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
60pub type USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `USR_MOSI_HIGHPART` reader - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
62pub type USR_MOSI_HIGHPART_R = crate::BitReader;
63#[doc = "Field `USR_MOSI_HIGHPART` writer - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
64pub type USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `USR_DUMMY_IDLE` reader - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
66pub type USR_DUMMY_IDLE_R = crate::BitReader;
67#[doc = "Field `USR_DUMMY_IDLE` writer - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
68pub type USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `USR_MOSI` reader - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
70pub type USR_MOSI_R = crate::BitReader;
71#[doc = "Field `USR_MOSI` writer - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
72pub type USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `USR_MISO` reader - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
74pub type USR_MISO_R = crate::BitReader;
75#[doc = "Field `USR_MISO` writer - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
76pub type USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `USR_DUMMY` reader - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
78pub type USR_DUMMY_R = crate::BitReader;
79#[doc = "Field `USR_DUMMY` writer - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
80pub type USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `USR_ADDR` reader - This bit enable the address phase of an operation. Can be configured in CONF state."]
82pub type USR_ADDR_R = crate::BitReader;
83#[doc = "Field `USR_ADDR` writer - This bit enable the address phase of an operation. Can be configured in CONF state."]
84pub type USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `USR_COMMAND` reader - This bit enable the command phase of an operation. Can be configured in CONF state."]
86pub type USR_COMMAND_R = crate::BitReader;
87#[doc = "Field `USR_COMMAND` writer - This bit enable the command phase of an operation. Can be configured in CONF state."]
88pub type USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>;
89impl R {
90 #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
91 #[inline(always)]
92 pub fn doutdin(&self) -> DOUTDIN_R {
93 DOUTDIN_R::new((self.bits & 1) != 0)
94 }
95 #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
96 #[inline(always)]
97 pub fn qpi_mode(&self) -> QPI_MODE_R {
98 QPI_MODE_R::new(((self.bits >> 3) & 1) != 0)
99 }
100 #[doc = "Bit 4 - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."]
101 #[inline(always)]
102 pub fn opi_mode(&self) -> OPI_MODE_R {
103 OPI_MODE_R::new(((self.bits >> 4) & 1) != 0)
104 }
105 #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
106 #[inline(always)]
107 pub fn tsck_i_edge(&self) -> TSCK_I_EDGE_R {
108 TSCK_I_EDGE_R::new(((self.bits >> 5) & 1) != 0)
109 }
110 #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
111 #[inline(always)]
112 pub fn cs_hold(&self) -> CS_HOLD_R {
113 CS_HOLD_R::new(((self.bits >> 6) & 1) != 0)
114 }
115 #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
116 #[inline(always)]
117 pub fn cs_setup(&self) -> CS_SETUP_R {
118 CS_SETUP_R::new(((self.bits >> 7) & 1) != 0)
119 }
120 #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
121 #[inline(always)]
122 pub fn rsck_i_edge(&self) -> RSCK_I_EDGE_R {
123 RSCK_I_EDGE_R::new(((self.bits >> 8) & 1) != 0)
124 }
125 #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
126 #[inline(always)]
127 pub fn ck_out_edge(&self) -> CK_OUT_EDGE_R {
128 CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0)
129 }
130 #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
131 #[inline(always)]
132 pub fn fwrite_dual(&self) -> FWRITE_DUAL_R {
133 FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0)
134 }
135 #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
136 #[inline(always)]
137 pub fn fwrite_quad(&self) -> FWRITE_QUAD_R {
138 FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0)
139 }
140 #[doc = "Bit 14 - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."]
141 #[inline(always)]
142 pub fn fwrite_oct(&self) -> FWRITE_OCT_R {
143 FWRITE_OCT_R::new(((self.bits >> 14) & 1) != 0)
144 }
145 #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
146 #[inline(always)]
147 pub fn usr_conf_nxt(&self) -> USR_CONF_NXT_R {
148 USR_CONF_NXT_R::new(((self.bits >> 15) & 1) != 0)
149 }
150 #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
151 #[inline(always)]
152 pub fn sio(&self) -> SIO_R {
153 SIO_R::new(((self.bits >> 17) & 1) != 0)
154 }
155 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
156 #[inline(always)]
157 pub fn usr_miso_highpart(&self) -> USR_MISO_HIGHPART_R {
158 USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0)
159 }
160 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
161 #[inline(always)]
162 pub fn usr_mosi_highpart(&self) -> USR_MOSI_HIGHPART_R {
163 USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0)
164 }
165 #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
166 #[inline(always)]
167 pub fn usr_dummy_idle(&self) -> USR_DUMMY_IDLE_R {
168 USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0)
169 }
170 #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
171 #[inline(always)]
172 pub fn usr_mosi(&self) -> USR_MOSI_R {
173 USR_MOSI_R::new(((self.bits >> 27) & 1) != 0)
174 }
175 #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
176 #[inline(always)]
177 pub fn usr_miso(&self) -> USR_MISO_R {
178 USR_MISO_R::new(((self.bits >> 28) & 1) != 0)
179 }
180 #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
181 #[inline(always)]
182 pub fn usr_dummy(&self) -> USR_DUMMY_R {
183 USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0)
184 }
185 #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."]
186 #[inline(always)]
187 pub fn usr_addr(&self) -> USR_ADDR_R {
188 USR_ADDR_R::new(((self.bits >> 30) & 1) != 0)
189 }
190 #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."]
191 #[inline(always)]
192 pub fn usr_command(&self) -> USR_COMMAND_R {
193 USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0)
194 }
195}
196#[cfg(feature = "impl-register-debug")]
197impl core::fmt::Debug for R {
198 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
199 f.debug_struct("USER")
200 .field("doutdin", &self.doutdin())
201 .field("qpi_mode", &self.qpi_mode())
202 .field("opi_mode", &self.opi_mode())
203 .field("tsck_i_edge", &self.tsck_i_edge())
204 .field("cs_hold", &self.cs_hold())
205 .field("cs_setup", &self.cs_setup())
206 .field("rsck_i_edge", &self.rsck_i_edge())
207 .field("ck_out_edge", &self.ck_out_edge())
208 .field("fwrite_dual", &self.fwrite_dual())
209 .field("fwrite_quad", &self.fwrite_quad())
210 .field("fwrite_oct", &self.fwrite_oct())
211 .field("usr_conf_nxt", &self.usr_conf_nxt())
212 .field("sio", &self.sio())
213 .field("usr_miso_highpart", &self.usr_miso_highpart())
214 .field("usr_mosi_highpart", &self.usr_mosi_highpart())
215 .field("usr_dummy_idle", &self.usr_dummy_idle())
216 .field("usr_mosi", &self.usr_mosi())
217 .field("usr_miso", &self.usr_miso())
218 .field("usr_dummy", &self.usr_dummy())
219 .field("usr_addr", &self.usr_addr())
220 .field("usr_command", &self.usr_command())
221 .finish()
222 }
223}
224impl W {
225 #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
226 #[inline(always)]
227 pub fn doutdin(&mut self) -> DOUTDIN_W<USER_SPEC> {
228 DOUTDIN_W::new(self, 0)
229 }
230 #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
231 #[inline(always)]
232 pub fn qpi_mode(&mut self) -> QPI_MODE_W<USER_SPEC> {
233 QPI_MODE_W::new(self, 3)
234 }
235 #[doc = "Bit 4 - Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state."]
236 #[inline(always)]
237 pub fn opi_mode(&mut self) -> OPI_MODE_W<USER_SPEC> {
238 OPI_MODE_W::new(self, 4)
239 }
240 #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
241 #[inline(always)]
242 pub fn tsck_i_edge(&mut self) -> TSCK_I_EDGE_W<USER_SPEC> {
243 TSCK_I_EDGE_W::new(self, 5)
244 }
245 #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
246 #[inline(always)]
247 pub fn cs_hold(&mut self) -> CS_HOLD_W<USER_SPEC> {
248 CS_HOLD_W::new(self, 6)
249 }
250 #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
251 #[inline(always)]
252 pub fn cs_setup(&mut self) -> CS_SETUP_W<USER_SPEC> {
253 CS_SETUP_W::new(self, 7)
254 }
255 #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
256 #[inline(always)]
257 pub fn rsck_i_edge(&mut self) -> RSCK_I_EDGE_W<USER_SPEC> {
258 RSCK_I_EDGE_W::new(self, 8)
259 }
260 #[doc = "Bit 9 - the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state."]
261 #[inline(always)]
262 pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
263 CK_OUT_EDGE_W::new(self, 9)
264 }
265 #[doc = "Bit 12 - In the write operations read-data phase apply 2 signals. Can be configured in CONF state."]
266 #[inline(always)]
267 pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
268 FWRITE_DUAL_W::new(self, 12)
269 }
270 #[doc = "Bit 13 - In the write operations read-data phase apply 4 signals. Can be configured in CONF state."]
271 #[inline(always)]
272 pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
273 FWRITE_QUAD_W::new(self, 13)
274 }
275 #[doc = "Bit 14 - In the write operations read-data phase apply 8 signals. Can be configured in CONF state."]
276 #[inline(always)]
277 pub fn fwrite_oct(&mut self) -> FWRITE_OCT_W<USER_SPEC> {
278 FWRITE_OCT_W::new(self, 14)
279 }
280 #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
281 #[inline(always)]
282 pub fn usr_conf_nxt(&mut self) -> USR_CONF_NXT_W<USER_SPEC> {
283 USR_CONF_NXT_W::new(self, 15)
284 }
285 #[doc = "Bit 17 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
286 #[inline(always)]
287 pub fn sio(&mut self) -> SIO_W<USER_SPEC> {
288 SIO_W::new(self, 17)
289 }
290 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
291 #[inline(always)]
292 pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<USER_SPEC> {
293 USR_MISO_HIGHPART_W::new(self, 24)
294 }
295 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state."]
296 #[inline(always)]
297 pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<USER_SPEC> {
298 USR_MOSI_HIGHPART_W::new(self, 25)
299 }
300 #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
301 #[inline(always)]
302 pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
303 USR_DUMMY_IDLE_W::new(self, 26)
304 }
305 #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
306 #[inline(always)]
307 pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
308 USR_MOSI_W::new(self, 27)
309 }
310 #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
311 #[inline(always)]
312 pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
313 USR_MISO_W::new(self, 28)
314 }
315 #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
316 #[inline(always)]
317 pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
318 USR_DUMMY_W::new(self, 29)
319 }
320 #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."]
321 #[inline(always)]
322 pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
323 USR_ADDR_W::new(self, 30)
324 }
325 #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."]
326 #[inline(always)]
327 pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
328 USR_COMMAND_W::new(self, 31)
329 }
330}
331#[doc = "SPI USER control register\n\nYou can [`read`](crate::Reg::read) this register and get [`user::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
332pub struct USER_SPEC;
333impl crate::RegisterSpec for USER_SPEC {
334 type Ux = u32;
335}
336#[doc = "`read()` method returns [`user::R`](R) reader structure"]
337impl crate::Readable for USER_SPEC {}
338#[doc = "`write(|w| ..)` method takes [`user::W`](W) writer structure"]
339impl crate::Writable for USER_SPEC {
340 type Safety = crate::Unsafe;
341 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
342 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
343}
344#[doc = "`reset()` method sets USER to value 0x8000_00c0"]
345impl crate::Resettable for USER_SPEC {
346 const RESET_VALUE: u32 = 0x8000_00c0;
347}