1#[doc = "Register `GUSBCFG` reader"]
2pub type R = crate::R<GUSBCFG_SPEC>;
3#[doc = "Register `GUSBCFG` writer"]
4pub type W = crate::W<GUSBCFG_SPEC>;
5#[doc = "Field `TOUTCAL` reader - "]
6pub type TOUTCAL_R = crate::FieldReader;
7#[doc = "Field `TOUTCAL` writer - "]
8pub type TOUTCAL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `PHYIF` reader - "]
10pub type PHYIF_R = crate::BitReader;
11#[doc = "Field `PHYIF` writer - "]
12pub type PHYIF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ULPI_UTMI_SEL` reader - "]
14pub type ULPI_UTMI_SEL_R = crate::BitReader;
15#[doc = "Field `FSINTF` reader - "]
16pub type FSINTF_R = crate::BitReader;
17#[doc = "Field `FSINTF` writer - "]
18pub type FSINTF_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `PHYSEL` reader - "]
20pub type PHYSEL_R = crate::BitReader;
21#[doc = "Field `SRPCAP` reader - "]
22pub type SRPCAP_R = crate::BitReader;
23#[doc = "Field `SRPCAP` writer - "]
24pub type SRPCAP_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `HNPCAP` reader - "]
26pub type HNPCAP_R = crate::BitReader;
27#[doc = "Field `HNPCAP` writer - "]
28pub type HNPCAP_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `USBTRDTIM` reader - "]
30pub type USBTRDTIM_R = crate::FieldReader;
31#[doc = "Field `USBTRDTIM` writer - "]
32pub type USBTRDTIM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
33#[doc = "Field `TERMSELDLPULSE` reader - "]
34pub type TERMSELDLPULSE_R = crate::BitReader;
35#[doc = "Field `TERMSELDLPULSE` writer - "]
36pub type TERMSELDLPULSE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TXENDDELAY` reader - "]
38pub type TXENDDELAY_R = crate::BitReader;
39#[doc = "Field `TXENDDELAY` writer - "]
40pub type TXENDDELAY_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FORCEHSTMODE` reader - "]
42pub type FORCEHSTMODE_R = crate::BitReader;
43#[doc = "Field `FORCEHSTMODE` writer - "]
44pub type FORCEHSTMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FORCEDEVMODE` reader - "]
46pub type FORCEDEVMODE_R = crate::BitReader;
47#[doc = "Field `FORCEDEVMODE` writer - "]
48pub type FORCEDEVMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CORRUPTTXPKT` reader - "]
50pub type CORRUPTTXPKT_R = crate::BitReader;
51#[doc = "Field `CORRUPTTXPKT` writer - "]
52pub type CORRUPTTXPKT_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54 #[doc = "Bits 0:2"]
55 #[inline(always)]
56 pub fn toutcal(&self) -> TOUTCAL_R {
57 TOUTCAL_R::new((self.bits & 7) as u8)
58 }
59 #[doc = "Bit 3"]
60 #[inline(always)]
61 pub fn phyif(&self) -> PHYIF_R {
62 PHYIF_R::new(((self.bits >> 3) & 1) != 0)
63 }
64 #[doc = "Bit 4"]
65 #[inline(always)]
66 pub fn ulpi_utmi_sel(&self) -> ULPI_UTMI_SEL_R {
67 ULPI_UTMI_SEL_R::new(((self.bits >> 4) & 1) != 0)
68 }
69 #[doc = "Bit 5"]
70 #[inline(always)]
71 pub fn fsintf(&self) -> FSINTF_R {
72 FSINTF_R::new(((self.bits >> 5) & 1) != 0)
73 }
74 #[doc = "Bit 6"]
75 #[inline(always)]
76 pub fn physel(&self) -> PHYSEL_R {
77 PHYSEL_R::new(((self.bits >> 6) & 1) != 0)
78 }
79 #[doc = "Bit 8"]
80 #[inline(always)]
81 pub fn srpcap(&self) -> SRPCAP_R {
82 SRPCAP_R::new(((self.bits >> 8) & 1) != 0)
83 }
84 #[doc = "Bit 9"]
85 #[inline(always)]
86 pub fn hnpcap(&self) -> HNPCAP_R {
87 HNPCAP_R::new(((self.bits >> 9) & 1) != 0)
88 }
89 #[doc = "Bits 10:13"]
90 #[inline(always)]
91 pub fn usbtrdtim(&self) -> USBTRDTIM_R {
92 USBTRDTIM_R::new(((self.bits >> 10) & 0x0f) as u8)
93 }
94 #[doc = "Bit 22"]
95 #[inline(always)]
96 pub fn termseldlpulse(&self) -> TERMSELDLPULSE_R {
97 TERMSELDLPULSE_R::new(((self.bits >> 22) & 1) != 0)
98 }
99 #[doc = "Bit 28"]
100 #[inline(always)]
101 pub fn txenddelay(&self) -> TXENDDELAY_R {
102 TXENDDELAY_R::new(((self.bits >> 28) & 1) != 0)
103 }
104 #[doc = "Bit 29"]
105 #[inline(always)]
106 pub fn forcehstmode(&self) -> FORCEHSTMODE_R {
107 FORCEHSTMODE_R::new(((self.bits >> 29) & 1) != 0)
108 }
109 #[doc = "Bit 30"]
110 #[inline(always)]
111 pub fn forcedevmode(&self) -> FORCEDEVMODE_R {
112 FORCEDEVMODE_R::new(((self.bits >> 30) & 1) != 0)
113 }
114 #[doc = "Bit 31"]
115 #[inline(always)]
116 pub fn corrupttxpkt(&self) -> CORRUPTTXPKT_R {
117 CORRUPTTXPKT_R::new(((self.bits >> 31) & 1) != 0)
118 }
119}
120#[cfg(feature = "impl-register-debug")]
121impl core::fmt::Debug for R {
122 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
123 f.debug_struct("GUSBCFG")
124 .field("toutcal", &self.toutcal())
125 .field("phyif", &self.phyif())
126 .field("ulpi_utmi_sel", &self.ulpi_utmi_sel())
127 .field("fsintf", &self.fsintf())
128 .field("physel", &self.physel())
129 .field("srpcap", &self.srpcap())
130 .field("hnpcap", &self.hnpcap())
131 .field("usbtrdtim", &self.usbtrdtim())
132 .field("termseldlpulse", &self.termseldlpulse())
133 .field("txenddelay", &self.txenddelay())
134 .field("forcehstmode", &self.forcehstmode())
135 .field("forcedevmode", &self.forcedevmode())
136 .field("corrupttxpkt", &self.corrupttxpkt())
137 .finish()
138 }
139}
140impl W {
141 #[doc = "Bits 0:2"]
142 #[inline(always)]
143 pub fn toutcal(&mut self) -> TOUTCAL_W<GUSBCFG_SPEC> {
144 TOUTCAL_W::new(self, 0)
145 }
146 #[doc = "Bit 3"]
147 #[inline(always)]
148 pub fn phyif(&mut self) -> PHYIF_W<GUSBCFG_SPEC> {
149 PHYIF_W::new(self, 3)
150 }
151 #[doc = "Bit 5"]
152 #[inline(always)]
153 pub fn fsintf(&mut self) -> FSINTF_W<GUSBCFG_SPEC> {
154 FSINTF_W::new(self, 5)
155 }
156 #[doc = "Bit 8"]
157 #[inline(always)]
158 pub fn srpcap(&mut self) -> SRPCAP_W<GUSBCFG_SPEC> {
159 SRPCAP_W::new(self, 8)
160 }
161 #[doc = "Bit 9"]
162 #[inline(always)]
163 pub fn hnpcap(&mut self) -> HNPCAP_W<GUSBCFG_SPEC> {
164 HNPCAP_W::new(self, 9)
165 }
166 #[doc = "Bits 10:13"]
167 #[inline(always)]
168 pub fn usbtrdtim(&mut self) -> USBTRDTIM_W<GUSBCFG_SPEC> {
169 USBTRDTIM_W::new(self, 10)
170 }
171 #[doc = "Bit 22"]
172 #[inline(always)]
173 pub fn termseldlpulse(&mut self) -> TERMSELDLPULSE_W<GUSBCFG_SPEC> {
174 TERMSELDLPULSE_W::new(self, 22)
175 }
176 #[doc = "Bit 28"]
177 #[inline(always)]
178 pub fn txenddelay(&mut self) -> TXENDDELAY_W<GUSBCFG_SPEC> {
179 TXENDDELAY_W::new(self, 28)
180 }
181 #[doc = "Bit 29"]
182 #[inline(always)]
183 pub fn forcehstmode(&mut self) -> FORCEHSTMODE_W<GUSBCFG_SPEC> {
184 FORCEHSTMODE_W::new(self, 29)
185 }
186 #[doc = "Bit 30"]
187 #[inline(always)]
188 pub fn forcedevmode(&mut self) -> FORCEDEVMODE_W<GUSBCFG_SPEC> {
189 FORCEDEVMODE_W::new(self, 30)
190 }
191 #[doc = "Bit 31"]
192 #[inline(always)]
193 pub fn corrupttxpkt(&mut self) -> CORRUPTTXPKT_W<GUSBCFG_SPEC> {
194 CORRUPTTXPKT_W::new(self, 31)
195 }
196}
197#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`gusbcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gusbcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
198pub struct GUSBCFG_SPEC;
199impl crate::RegisterSpec for GUSBCFG_SPEC {
200 type Ux = u32;
201}
202#[doc = "`read()` method returns [`gusbcfg::R`](R) reader structure"]
203impl crate::Readable for GUSBCFG_SPEC {}
204#[doc = "`write(|w| ..)` method takes [`gusbcfg::W`](W) writer structure"]
205impl crate::Writable for GUSBCFG_SPEC {
206 type Safety = crate::Unsafe;
207}
208#[doc = "`reset()` method sets GUSBCFG to value 0x1440"]
209impl crate::Resettable for GUSBCFG_SPEC {
210 const RESET_VALUE: u32 = 0x1440;
211}