1#[doc = "Register `CMD` reader"]
2pub type R = crate::R<CMD_SPEC>;
3#[doc = "Register `CMD` writer"]
4pub type W = crate::W<CMD_SPEC>;
5#[doc = "Field `FLASH_PE` reader - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable."]
6pub type FLASH_PE_R = crate::BitReader;
7#[doc = "Field `FLASH_PE` writer - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable."]
8pub type FLASH_PE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `USR` reader - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
10pub type USR_R = crate::BitReader;
11#[doc = "Field `USR` writer - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
12pub type USR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FLASH_HPM` reader - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."]
14pub type FLASH_HPM_R = crate::BitReader;
15#[doc = "Field `FLASH_HPM` writer - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."]
16pub type FLASH_HPM_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FLASH_RES` reader - This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."]
18pub type FLASH_RES_R = crate::BitReader;
19#[doc = "Field `FLASH_RES` writer - This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."]
20pub type FLASH_RES_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FLASH_DP` reader - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
22pub type FLASH_DP_R = crate::BitReader;
23#[doc = "Field `FLASH_DP` writer - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
24pub type FLASH_DP_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FLASH_CE` reader - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
26pub type FLASH_CE_R = crate::BitReader;
27#[doc = "Field `FLASH_CE` writer - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
28pub type FLASH_CE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FLASH_BE` reader - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
30pub type FLASH_BE_R = crate::BitReader;
31#[doc = "Field `FLASH_BE` writer - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
32pub type FLASH_BE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FLASH_SE` reader - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
34pub type FLASH_SE_R = crate::BitReader;
35#[doc = "Field `FLASH_SE` writer - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
36pub type FLASH_SE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FLASH_PP` reader - Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."]
38pub type FLASH_PP_R = crate::BitReader;
39#[doc = "Field `FLASH_PP` writer - Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."]
40pub type FLASH_PP_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FLASH_WRSR` reader - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
42pub type FLASH_WRSR_R = crate::BitReader;
43#[doc = "Field `FLASH_WRSR` writer - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
44pub type FLASH_WRSR_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FLASH_RDSR` reader - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
46pub type FLASH_RDSR_R = crate::BitReader;
47#[doc = "Field `FLASH_RDSR` writer - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
48pub type FLASH_RDSR_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `FLASH_RDID` reader - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
50pub type FLASH_RDID_R = crate::BitReader;
51#[doc = "Field `FLASH_RDID` writer - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
52pub type FLASH_RDID_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `FLASH_WRDI` reader - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
54pub type FLASH_WRDI_R = crate::BitReader;
55#[doc = "Field `FLASH_WRDI` writer - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
56pub type FLASH_WRDI_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `FLASH_WREN` reader - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
58pub type FLASH_WREN_R = crate::BitReader;
59#[doc = "Field `FLASH_WREN` writer - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
60pub type FLASH_WREN_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `FLASH_READ` reader - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
62pub type FLASH_READ_R = crate::BitReader;
63#[doc = "Field `FLASH_READ` writer - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
64pub type FLASH_READ_W<'a, REG> = crate::BitWriter<'a, REG>;
65impl R {
66 #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable."]
67 #[inline(always)]
68 pub fn flash_pe(&self) -> FLASH_PE_R {
69 FLASH_PE_R::new(((self.bits >> 17) & 1) != 0)
70 }
71 #[doc = "Bit 18 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
72 #[inline(always)]
73 pub fn usr(&self) -> USR_R {
74 USR_R::new(((self.bits >> 18) & 1) != 0)
75 }
76 #[doc = "Bit 19 - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."]
77 #[inline(always)]
78 pub fn flash_hpm(&self) -> FLASH_HPM_R {
79 FLASH_HPM_R::new(((self.bits >> 19) & 1) != 0)
80 }
81 #[doc = "Bit 20 - This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."]
82 #[inline(always)]
83 pub fn flash_res(&self) -> FLASH_RES_R {
84 FLASH_RES_R::new(((self.bits >> 20) & 1) != 0)
85 }
86 #[doc = "Bit 21 - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
87 #[inline(always)]
88 pub fn flash_dp(&self) -> FLASH_DP_R {
89 FLASH_DP_R::new(((self.bits >> 21) & 1) != 0)
90 }
91 #[doc = "Bit 22 - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
92 #[inline(always)]
93 pub fn flash_ce(&self) -> FLASH_CE_R {
94 FLASH_CE_R::new(((self.bits >> 22) & 1) != 0)
95 }
96 #[doc = "Bit 23 - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
97 #[inline(always)]
98 pub fn flash_be(&self) -> FLASH_BE_R {
99 FLASH_BE_R::new(((self.bits >> 23) & 1) != 0)
100 }
101 #[doc = "Bit 24 - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
102 #[inline(always)]
103 pub fn flash_se(&self) -> FLASH_SE_R {
104 FLASH_SE_R::new(((self.bits >> 24) & 1) != 0)
105 }
106 #[doc = "Bit 25 - Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."]
107 #[inline(always)]
108 pub fn flash_pp(&self) -> FLASH_PP_R {
109 FLASH_PP_R::new(((self.bits >> 25) & 1) != 0)
110 }
111 #[doc = "Bit 26 - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
112 #[inline(always)]
113 pub fn flash_wrsr(&self) -> FLASH_WRSR_R {
114 FLASH_WRSR_R::new(((self.bits >> 26) & 1) != 0)
115 }
116 #[doc = "Bit 27 - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
117 #[inline(always)]
118 pub fn flash_rdsr(&self) -> FLASH_RDSR_R {
119 FLASH_RDSR_R::new(((self.bits >> 27) & 1) != 0)
120 }
121 #[doc = "Bit 28 - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
122 #[inline(always)]
123 pub fn flash_rdid(&self) -> FLASH_RDID_R {
124 FLASH_RDID_R::new(((self.bits >> 28) & 1) != 0)
125 }
126 #[doc = "Bit 29 - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
127 #[inline(always)]
128 pub fn flash_wrdi(&self) -> FLASH_WRDI_R {
129 FLASH_WRDI_R::new(((self.bits >> 29) & 1) != 0)
130 }
131 #[doc = "Bit 30 - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
132 #[inline(always)]
133 pub fn flash_wren(&self) -> FLASH_WREN_R {
134 FLASH_WREN_R::new(((self.bits >> 30) & 1) != 0)
135 }
136 #[doc = "Bit 31 - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
137 #[inline(always)]
138 pub fn flash_read(&self) -> FLASH_READ_R {
139 FLASH_READ_R::new(((self.bits >> 31) & 1) != 0)
140 }
141}
142#[cfg(feature = "impl-register-debug")]
143impl core::fmt::Debug for R {
144 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
145 f.debug_struct("CMD")
146 .field("flash_pe", &self.flash_pe())
147 .field("usr", &self.usr())
148 .field("flash_hpm", &self.flash_hpm())
149 .field("flash_res", &self.flash_res())
150 .field("flash_dp", &self.flash_dp())
151 .field("flash_ce", &self.flash_ce())
152 .field("flash_be", &self.flash_be())
153 .field("flash_se", &self.flash_se())
154 .field("flash_pp", &self.flash_pp())
155 .field("flash_wrsr", &self.flash_wrsr())
156 .field("flash_rdsr", &self.flash_rdsr())
157 .field("flash_rdid", &self.flash_rdid())
158 .field("flash_wrdi", &self.flash_wrdi())
159 .field("flash_wren", &self.flash_wren())
160 .field("flash_read", &self.flash_read())
161 .finish()
162 }
163}
164impl W {
165 #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable."]
166 #[inline(always)]
167 pub fn flash_pe(&mut self) -> FLASH_PE_W<CMD_SPEC> {
168 FLASH_PE_W::new(self, 17)
169 }
170 #[doc = "Bit 18 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
171 #[inline(always)]
172 pub fn usr(&mut self) -> USR_W<CMD_SPEC> {
173 USR_W::new(self, 18)
174 }
175 #[doc = "Bit 19 - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable."]
176 #[inline(always)]
177 pub fn flash_hpm(&mut self) -> FLASH_HPM_W<CMD_SPEC> {
178 FLASH_HPM_W::new(self, 19)
179 }
180 #[doc = "Bit 20 - This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable."]
181 #[inline(always)]
182 pub fn flash_res(&mut self) -> FLASH_RES_W<CMD_SPEC> {
183 FLASH_RES_W::new(self, 20)
184 }
185 #[doc = "Bit 21 - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
186 #[inline(always)]
187 pub fn flash_dp(&mut self) -> FLASH_DP_W<CMD_SPEC> {
188 FLASH_DP_W::new(self, 21)
189 }
190 #[doc = "Bit 22 - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
191 #[inline(always)]
192 pub fn flash_ce(&mut self) -> FLASH_CE_W<CMD_SPEC> {
193 FLASH_CE_W::new(self, 22)
194 }
195 #[doc = "Bit 23 - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
196 #[inline(always)]
197 pub fn flash_be(&mut self) -> FLASH_BE_W<CMD_SPEC> {
198 FLASH_BE_W::new(self, 23)
199 }
200 #[doc = "Bit 24 - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
201 #[inline(always)]
202 pub fn flash_se(&mut self) -> FLASH_SE_W<CMD_SPEC> {
203 FLASH_SE_W::new(self, 24)
204 }
205 #[doc = "Bit 25 - Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable."]
206 #[inline(always)]
207 pub fn flash_pp(&mut self) -> FLASH_PP_W<CMD_SPEC> {
208 FLASH_PP_W::new(self, 25)
209 }
210 #[doc = "Bit 26 - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
211 #[inline(always)]
212 pub fn flash_wrsr(&mut self) -> FLASH_WRSR_W<CMD_SPEC> {
213 FLASH_WRSR_W::new(self, 26)
214 }
215 #[doc = "Bit 27 - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
216 #[inline(always)]
217 pub fn flash_rdsr(&mut self) -> FLASH_RDSR_W<CMD_SPEC> {
218 FLASH_RDSR_W::new(self, 27)
219 }
220 #[doc = "Bit 28 - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
221 #[inline(always)]
222 pub fn flash_rdid(&mut self) -> FLASH_RDID_W<CMD_SPEC> {
223 FLASH_RDID_W::new(self, 28)
224 }
225 #[doc = "Bit 29 - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
226 #[inline(always)]
227 pub fn flash_wrdi(&mut self) -> FLASH_WRDI_W<CMD_SPEC> {
228 FLASH_WRDI_W::new(self, 29)
229 }
230 #[doc = "Bit 30 - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
231 #[inline(always)]
232 pub fn flash_wren(&mut self) -> FLASH_WREN_W<CMD_SPEC> {
233 FLASH_WREN_W::new(self, 30)
234 }
235 #[doc = "Bit 31 - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable."]
236 #[inline(always)]
237 pub fn flash_read(&mut self) -> FLASH_READ_W<CMD_SPEC> {
238 FLASH_READ_W::new(self, 31)
239 }
240}
241#[doc = "SPI1 memory command register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
242pub struct CMD_SPEC;
243impl crate::RegisterSpec for CMD_SPEC {
244 type Ux = u32;
245}
246#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
247impl crate::Readable for CMD_SPEC {}
248#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
249impl crate::Writable for CMD_SPEC {
250 type Safety = crate::Unsafe;
251 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
252 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
253}
254#[doc = "`reset()` method sets CMD to value 0"]
255impl crate::Resettable for CMD_SPEC {
256 const RESET_VALUE: u32 = 0;
257}