1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 cmd: CMD,
6 addr: ADDR,
7 ctrl: CTRL,
8 ctrl1: CTRL1,
9 ctrl2: CTRL2,
10 clock: CLOCK,
11 user: USER,
12 user1: USER1,
13 user2: USER2,
14 mosi_dlen: MOSI_DLEN,
15 miso_dlen: MISO_DLEN,
16 rd_status: RD_STATUS,
17 ext_addr: EXT_ADDR,
18 misc: MISC,
19 tx_crc: TX_CRC,
20 cache_fctrl: CACHE_FCTRL,
21 _reserved16: [u8; 0x14],
22 fsm: FSM,
23 w: [W; 16],
24 flash_waiti_ctrl: FLASH_WAITI_CTRL,
25 flash_sus_cmd: FLASH_SUS_CMD,
26 flash_sus_ctrl: FLASH_SUS_CTRL,
27 sus_status: SUS_STATUS,
28 timing_cali: TIMING_CALI,
29 _reserved23: [u8; 0x34],
30 ddr: DDR,
31 _reserved24: [u8; 0x04],
32 clock_gate: CLOCK_GATE,
33 _reserved25: [u8; 0x04],
34 int_ena: INT_ENA,
35 int_clr: INT_CLR,
36 int_raw: INT_RAW,
37 int_st: INT_ST,
38 _reserved29: [u8; 0x02fc],
39 date: DATE,
40}
41impl RegisterBlock {
42 #[doc = "0x00 - SPI1 memory command register"]
43 #[inline(always)]
44 pub const fn cmd(&self) -> &CMD {
45 &self.cmd
46 }
47 #[doc = "0x04 - SPI1 address register"]
48 #[inline(always)]
49 pub const fn addr(&self) -> &ADDR {
50 &self.addr
51 }
52 #[doc = "0x08 - SPI1 control register"]
53 #[inline(always)]
54 pub const fn ctrl(&self) -> &CTRL {
55 &self.ctrl
56 }
57 #[doc = "0x0c - SPI1 control1 register"]
58 #[inline(always)]
59 pub const fn ctrl1(&self) -> &CTRL1 {
60 &self.ctrl1
61 }
62 #[doc = "0x10 - SPI1 control2 register"]
63 #[inline(always)]
64 pub const fn ctrl2(&self) -> &CTRL2 {
65 &self.ctrl2
66 }
67 #[doc = "0x14 - SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM."]
68 #[inline(always)]
69 pub const fn clock(&self) -> &CLOCK {
70 &self.clock
71 }
72 #[doc = "0x18 - SPI1 user register."]
73 #[inline(always)]
74 pub const fn user(&self) -> &USER {
75 &self.user
76 }
77 #[doc = "0x1c - SPI1 user1 register."]
78 #[inline(always)]
79 pub const fn user1(&self) -> &USER1 {
80 &self.user1
81 }
82 #[doc = "0x20 - SPI1 user2 register."]
83 #[inline(always)]
84 pub const fn user2(&self) -> &USER2 {
85 &self.user2
86 }
87 #[doc = "0x24 - SPI1 write-data bit length register."]
88 #[inline(always)]
89 pub const fn mosi_dlen(&self) -> &MOSI_DLEN {
90 &self.mosi_dlen
91 }
92 #[doc = "0x28 - SPI1 read-data bit length register."]
93 #[inline(always)]
94 pub const fn miso_dlen(&self) -> &MISO_DLEN {
95 &self.miso_dlen
96 }
97 #[doc = "0x2c - SPI1 read control register."]
98 #[inline(always)]
99 pub const fn rd_status(&self) -> &RD_STATUS {
100 &self.rd_status
101 }
102 #[doc = "0x30 - SPI1 extended address register."]
103 #[inline(always)]
104 pub const fn ext_addr(&self) -> &EXT_ADDR {
105 &self.ext_addr
106 }
107 #[doc = "0x34 - SPI1 misc register."]
108 #[inline(always)]
109 pub const fn misc(&self) -> &MISC {
110 &self.misc
111 }
112 #[doc = "0x38 - SPI1 CRC data register."]
113 #[inline(always)]
114 pub const fn tx_crc(&self) -> &TX_CRC {
115 &self.tx_crc
116 }
117 #[doc = "0x3c - SPI1 bit mode control register."]
118 #[inline(always)]
119 pub const fn cache_fctrl(&self) -> &CACHE_FCTRL {
120 &self.cache_fctrl
121 }
122 #[doc = "0x54 - SPI1 state machine(FSM) status register."]
123 #[inline(always)]
124 pub const fn fsm(&self) -> &FSM {
125 &self.fsm
126 }
127 #[doc = "0x58..0x98 - SPI1 memory data buffer%s"]
128 #[inline(always)]
129 pub const fn w(&self, n: usize) -> &W {
130 &self.w[n]
131 }
132 #[doc = "Iterator for array of:"]
133 #[doc = "0x58..0x98 - SPI1 memory data buffer%s"]
134 #[inline(always)]
135 pub fn w_iter(&self) -> impl Iterator<Item = &W> {
136 self.w.iter()
137 }
138 #[doc = "0x98 - SPI1 wait idle control register"]
139 #[inline(always)]
140 pub const fn flash_waiti_ctrl(&self) -> &FLASH_WAITI_CTRL {
141 &self.flash_waiti_ctrl
142 }
143 #[doc = "0x9c - SPI1 flash suspend control register"]
144 #[inline(always)]
145 pub const fn flash_sus_cmd(&self) -> &FLASH_SUS_CMD {
146 &self.flash_sus_cmd
147 }
148 #[doc = "0xa0 - SPI1 flash suspend command register"]
149 #[inline(always)]
150 pub const fn flash_sus_ctrl(&self) -> &FLASH_SUS_CTRL {
151 &self.flash_sus_ctrl
152 }
153 #[doc = "0xa4 - SPI1 flash suspend status register"]
154 #[inline(always)]
155 pub const fn sus_status(&self) -> &SUS_STATUS {
156 &self.sus_status
157 }
158 #[doc = "0xa8 - SPI1 timing compensation register when accesses to flash or Ext_RAM."]
159 #[inline(always)]
160 pub const fn timing_cali(&self) -> &TIMING_CALI {
161 &self.timing_cali
162 }
163 #[doc = "0xe0 - SPI1 DDR control register"]
164 #[inline(always)]
165 pub const fn ddr(&self) -> &DDR {
166 &self.ddr
167 }
168 #[doc = "0xe8 - SPI1 clk_gate register"]
169 #[inline(always)]
170 pub const fn clock_gate(&self) -> &CLOCK_GATE {
171 &self.clock_gate
172 }
173 #[doc = "0xf0 - SPI1 interrupt enable register"]
174 #[inline(always)]
175 pub const fn int_ena(&self) -> &INT_ENA {
176 &self.int_ena
177 }
178 #[doc = "0xf4 - SPI1 interrupt clear register"]
179 #[inline(always)]
180 pub const fn int_clr(&self) -> &INT_CLR {
181 &self.int_clr
182 }
183 #[doc = "0xf8 - SPI1 interrupt raw register"]
184 #[inline(always)]
185 pub const fn int_raw(&self) -> &INT_RAW {
186 &self.int_raw
187 }
188 #[doc = "0xfc - SPI1 interrupt status register"]
189 #[inline(always)]
190 pub const fn int_st(&self) -> &INT_ST {
191 &self.int_st
192 }
193 #[doc = "0x3fc - SPI0 version control register"]
194 #[inline(always)]
195 pub const fn date(&self) -> &DATE {
196 &self.date
197 }
198}
199#[doc = "CMD (rw) register accessor: SPI1 memory command register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"]
200pub type CMD = crate::Reg<cmd::CMD_SPEC>;
201#[doc = "SPI1 memory command register"]
202pub mod cmd;
203#[doc = "ADDR (rw) register accessor: SPI1 address register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`] module"]
204pub type ADDR = crate::Reg<addr::ADDR_SPEC>;
205#[doc = "SPI1 address register"]
206pub mod addr;
207#[doc = "CTRL (rw) register accessor: SPI1 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
208pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
209#[doc = "SPI1 control register"]
210pub mod ctrl;
211#[doc = "CTRL1 (rw) register accessor: SPI1 control1 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"]
212pub type CTRL1 = crate::Reg<ctrl1::CTRL1_SPEC>;
213#[doc = "SPI1 control1 register"]
214pub mod ctrl1;
215#[doc = "CTRL2 (rw) register accessor: SPI1 control2 register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl2`] module"]
216pub type CTRL2 = crate::Reg<ctrl2::CTRL2_SPEC>;
217#[doc = "SPI1 control2 register"]
218pub mod ctrl2;
219#[doc = "CLOCK (rw) register accessor: SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM.\n\nYou can [`read`](crate::Reg::read) this register and get [`clock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock`] module"]
220pub type CLOCK = crate::Reg<clock::CLOCK_SPEC>;
221#[doc = "SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM."]
222pub mod clock;
223#[doc = "USER (rw) register accessor: SPI1 user register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@user`] module"]
224pub type USER = crate::Reg<user::USER_SPEC>;
225#[doc = "SPI1 user register."]
226pub mod user;
227#[doc = "USER1 (rw) register accessor: SPI1 user1 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@user1`] module"]
228pub type USER1 = crate::Reg<user1::USER1_SPEC>;
229#[doc = "SPI1 user1 register."]
230pub mod user1;
231#[doc = "USER2 (rw) register accessor: SPI1 user2 register.\n\nYou can [`read`](crate::Reg::read) this register and get [`user2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@user2`] module"]
232pub type USER2 = crate::Reg<user2::USER2_SPEC>;
233#[doc = "SPI1 user2 register."]
234pub mod user2;
235#[doc = "MOSI_DLEN (rw) register accessor: SPI1 write-data bit length register.\n\nYou can [`read`](crate::Reg::read) this register and get [`mosi_dlen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mosi_dlen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mosi_dlen`] module"]
236pub type MOSI_DLEN = crate::Reg<mosi_dlen::MOSI_DLEN_SPEC>;
237#[doc = "SPI1 write-data bit length register."]
238pub mod mosi_dlen;
239#[doc = "MISO_DLEN (rw) register accessor: SPI1 read-data bit length register.\n\nYou can [`read`](crate::Reg::read) this register and get [`miso_dlen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`miso_dlen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miso_dlen`] module"]
240pub type MISO_DLEN = crate::Reg<miso_dlen::MISO_DLEN_SPEC>;
241#[doc = "SPI1 read-data bit length register."]
242pub mod miso_dlen;
243#[doc = "RD_STATUS (rw) register accessor: SPI1 read control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`rd_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rd_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_status`] module"]
244pub type RD_STATUS = crate::Reg<rd_status::RD_STATUS_SPEC>;
245#[doc = "SPI1 read control register."]
246pub mod rd_status;
247#[doc = "EXT_ADDR (rw) register accessor: SPI1 extended address register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_addr`] module"]
248pub type EXT_ADDR = crate::Reg<ext_addr::EXT_ADDR_SPEC>;
249#[doc = "SPI1 extended address register."]
250pub mod ext_addr;
251#[doc = "MISC (rw) register accessor: SPI1 misc register.\n\nYou can [`read`](crate::Reg::read) this register and get [`misc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc`] module"]
252pub type MISC = crate::Reg<misc::MISC_SPEC>;
253#[doc = "SPI1 misc register."]
254pub mod misc;
255#[doc = "TX_CRC (r) register accessor: SPI1 CRC data register.\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_crc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_crc`] module"]
256pub type TX_CRC = crate::Reg<tx_crc::TX_CRC_SPEC>;
257#[doc = "SPI1 CRC data register."]
258pub mod tx_crc;
259#[doc = "CACHE_FCTRL (rw) register accessor: SPI1 bit mode control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_fctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_fctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_fctrl`] module"]
260pub type CACHE_FCTRL = crate::Reg<cache_fctrl::CACHE_FCTRL_SPEC>;
261#[doc = "SPI1 bit mode control register."]
262pub mod cache_fctrl;
263#[doc = "FSM (r) register accessor: SPI1 state machine(FSM) status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`fsm::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsm`] module"]
264pub type FSM = crate::Reg<fsm::FSM_SPEC>;
265#[doc = "SPI1 state machine(FSM) status register."]
266pub mod fsm;
267#[doc = "W (rw) register accessor: SPI1 memory data buffer%s\n\nYou can [`read`](crate::Reg::read) this register and get [`w::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`w::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@w`] module"]
268pub type W = crate::Reg<w::W_SPEC>;
269#[doc = "SPI1 memory data buffer%s"]
270pub mod w;
271#[doc = "FLASH_WAITI_CTRL (rw) register accessor: SPI1 wait idle control register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_waiti_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_waiti_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_waiti_ctrl`] module"]
272pub type FLASH_WAITI_CTRL = crate::Reg<flash_waiti_ctrl::FLASH_WAITI_CTRL_SPEC>;
273#[doc = "SPI1 wait idle control register"]
274pub mod flash_waiti_ctrl;
275#[doc = "FLASH_SUS_CMD (rw) register accessor: SPI1 flash suspend control register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_sus_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_sus_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_sus_cmd`] module"]
276pub type FLASH_SUS_CMD = crate::Reg<flash_sus_cmd::FLASH_SUS_CMD_SPEC>;
277#[doc = "SPI1 flash suspend control register"]
278pub mod flash_sus_cmd;
279#[doc = "FLASH_SUS_CTRL (rw) register accessor: SPI1 flash suspend command register\n\nYou can [`read`](crate::Reg::read) this register and get [`flash_sus_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_sus_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flash_sus_ctrl`] module"]
280pub type FLASH_SUS_CTRL = crate::Reg<flash_sus_ctrl::FLASH_SUS_CTRL_SPEC>;
281#[doc = "SPI1 flash suspend command register"]
282pub mod flash_sus_ctrl;
283#[doc = "SUS_STATUS (rw) register accessor: SPI1 flash suspend status register\n\nYou can [`read`](crate::Reg::read) this register and get [`sus_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sus_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sus_status`] module"]
284pub type SUS_STATUS = crate::Reg<sus_status::SUS_STATUS_SPEC>;
285#[doc = "SPI1 flash suspend status register"]
286pub mod sus_status;
287#[doc = "TIMING_CALI (rw) register accessor: SPI1 timing compensation register when accesses to flash or Ext_RAM.\n\nYou can [`read`](crate::Reg::read) this register and get [`timing_cali::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timing_cali::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timing_cali`] module"]
288pub type TIMING_CALI = crate::Reg<timing_cali::TIMING_CALI_SPEC>;
289#[doc = "SPI1 timing compensation register when accesses to flash or Ext_RAM."]
290pub mod timing_cali;
291#[doc = "DDR (rw) register accessor: SPI1 DDR control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ddr`] module"]
292pub type DDR = crate::Reg<ddr::DDR_SPEC>;
293#[doc = "SPI1 DDR control register"]
294pub mod ddr;
295#[doc = "CLOCK_GATE (rw) register accessor: SPI1 clk_gate register\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"]
296pub type CLOCK_GATE = crate::Reg<clock_gate::CLOCK_GATE_SPEC>;
297#[doc = "SPI1 clk_gate register"]
298pub mod clock_gate;
299#[doc = "INT_ENA (rw) register accessor: SPI1 interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
300pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
301#[doc = "SPI1 interrupt enable register"]
302pub mod int_ena;
303#[doc = "INT_CLR (w) register accessor: SPI1 interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
304pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
305#[doc = "SPI1 interrupt clear register"]
306pub mod int_clr;
307#[doc = "INT_RAW (rw) register accessor: SPI1 interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
308pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
309#[doc = "SPI1 interrupt raw register"]
310pub mod int_raw;
311#[doc = "INT_ST (r) register accessor: SPI1 interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
312pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
313#[doc = "SPI1 interrupt status register"]
314pub mod int_st;
315#[doc = "DATE (rw) register accessor: SPI0 version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
316pub type DATE = crate::Reg<date::DATE_SPEC>;
317#[doc = "SPI0 version control register"]
318pub mod date;