1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 ch: [CH; 5],
6 ahb_test: AHB_TEST,
7 pd_conf: PD_CONF,
8 misc_conf: MISC_CONF,
9 in_sram_size_ch: (),
10 _reserved5: [u8; 0x04],
11 out_sram_size_ch: (),
12 _reserved6: [u8; 0x24],
13 extmem_reject_addr: EXTMEM_REJECT_ADDR,
14 extmem_reject_st: EXTMEM_REJECT_ST,
15 extmem_reject_int_raw: EXTMEM_REJECT_INT_RAW,
16 extmem_reject_int_st: EXTMEM_REJECT_INT_ST,
17 extmem_reject_int_ena: EXTMEM_REJECT_INT_ENA,
18 extmem_reject_int_clr: EXTMEM_REJECT_INT_CLR,
19 date: DATE,
20}
21impl RegisterBlock {
22 #[doc = "0x00..0x3c0 - Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_WIGHT_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_WIGHT_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?"]
23 #[inline(always)]
24 pub const fn ch(&self, n: usize) -> &CH {
25 &self.ch[n]
26 }
27 #[doc = "Iterator for array of:"]
28 #[doc = "0x00..0x3c0 - Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_WIGHT_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_WIGHT_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?"]
29 #[inline(always)]
30 pub fn ch_iter(&self) -> impl Iterator<Item = &CH> {
31 self.ch.iter()
32 }
33 #[doc = "0x3c0 - reserved"]
34 #[inline(always)]
35 pub const fn ahb_test(&self) -> &AHB_TEST {
36 &self.ahb_test
37 }
38 #[doc = "0x3c4 - reserved"]
39 #[inline(always)]
40 pub const fn pd_conf(&self) -> &PD_CONF {
41 &self.pd_conf
42 }
43 #[doc = "0x3c8 - MISC register"]
44 #[inline(always)]
45 pub const fn misc_conf(&self) -> &MISC_CONF {
46 &self.misc_conf
47 }
48 #[doc = "0x3cc..0x3e0 - Receive L2 FIFO depth of Rx channel 0"]
49 #[inline(always)]
50 pub const fn in_sram_size_ch(&self, n: usize) -> &IN_SRAM_SIZE_CH {
51 #[allow(clippy::no_effect)]
52 [(); 5][n];
53 unsafe {
54 &*core::ptr::from_ref(self)
55 .cast::<u8>()
56 .add(972)
57 .add(8 * n)
58 .cast()
59 }
60 }
61 #[doc = "Iterator for array of:"]
62 #[doc = "0x3cc..0x3e0 - Receive L2 FIFO depth of Rx channel 0"]
63 #[inline(always)]
64 pub fn in_sram_size_ch_iter(&self) -> impl Iterator<Item = &IN_SRAM_SIZE_CH> {
65 (0..5).map(move |n| unsafe {
66 &*core::ptr::from_ref(self)
67 .cast::<u8>()
68 .add(972)
69 .add(8 * n)
70 .cast()
71 })
72 }
73 #[doc = "0x3d0..0x3e4 - Transmit L2 FIFO depth of Tx channel 0"]
74 #[inline(always)]
75 pub const fn out_sram_size_ch(&self, n: usize) -> &OUT_SRAM_SIZE_CH {
76 #[allow(clippy::no_effect)]
77 [(); 5][n];
78 unsafe {
79 &*core::ptr::from_ref(self)
80 .cast::<u8>()
81 .add(976)
82 .add(8 * n)
83 .cast()
84 }
85 }
86 #[doc = "Iterator for array of:"]
87 #[doc = "0x3d0..0x3e4 - Transmit L2 FIFO depth of Tx channel 0"]
88 #[inline(always)]
89 pub fn out_sram_size_ch_iter(&self) -> impl Iterator<Item = &OUT_SRAM_SIZE_CH> {
90 (0..5).map(move |n| unsafe {
91 &*core::ptr::from_ref(self)
92 .cast::<u8>()
93 .add(976)
94 .add(8 * n)
95 .cast()
96 })
97 }
98 #[doc = "0x3f4 - Reject address accessing external RAM"]
99 #[inline(always)]
100 pub const fn extmem_reject_addr(&self) -> &EXTMEM_REJECT_ADDR {
101 &self.extmem_reject_addr
102 }
103 #[doc = "0x3f8 - Reject status accessing external RAM"]
104 #[inline(always)]
105 pub const fn extmem_reject_st(&self) -> &EXTMEM_REJECT_ST {
106 &self.extmem_reject_st
107 }
108 #[doc = "0x3fc - Raw interrupt status of external RAM permission"]
109 #[inline(always)]
110 pub const fn extmem_reject_int_raw(&self) -> &EXTMEM_REJECT_INT_RAW {
111 &self.extmem_reject_int_raw
112 }
113 #[doc = "0x400 - Masked interrupt status of external RAM permission"]
114 #[inline(always)]
115 pub const fn extmem_reject_int_st(&self) -> &EXTMEM_REJECT_INT_ST {
116 &self.extmem_reject_int_st
117 }
118 #[doc = "0x404 - Interrupt enable bits of external RAM permission"]
119 #[inline(always)]
120 pub const fn extmem_reject_int_ena(&self) -> &EXTMEM_REJECT_INT_ENA {
121 &self.extmem_reject_int_ena
122 }
123 #[doc = "0x408 - Interrupt clear bits of external RAM permission"]
124 #[inline(always)]
125 pub const fn extmem_reject_int_clr(&self) -> &EXTMEM_REJECT_INT_CLR {
126 &self.extmem_reject_int_clr
127 }
128 #[doc = "0x40c - Version control register"]
129 #[inline(always)]
130 pub const fn date(&self) -> &DATE {
131 &self.date
132 }
133}
134#[doc = "Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_WIGHT_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_WIGHT_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?"]
135pub use self::ch::CH;
136#[doc = r"Cluster"]
137#[doc = "Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_WIGHT_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_WIGHT_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?"]
138pub mod ch;
139#[doc = "AHB_TEST (rw) register accessor: reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_test::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_test::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_test`] module"]
140pub type AHB_TEST = crate::Reg<ahb_test::AHB_TEST_SPEC>;
141#[doc = "reserved"]
142pub mod ahb_test;
143#[doc = "PD_CONF (rw) register accessor: reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pd_conf`] module"]
144pub type PD_CONF = crate::Reg<pd_conf::PD_CONF_SPEC>;
145#[doc = "reserved"]
146pub mod pd_conf;
147#[doc = "MISC_CONF (rw) register accessor: MISC register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc_conf`] module"]
148pub type MISC_CONF = crate::Reg<misc_conf::MISC_CONF_SPEC>;
149#[doc = "MISC register"]
150pub mod misc_conf;
151#[doc = "IN_SRAM_SIZE_CH (rw) register accessor: Receive L2 FIFO depth of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sram_size_ch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sram_size_ch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_sram_size_ch`] module"]
152pub type IN_SRAM_SIZE_CH = crate::Reg<in_sram_size_ch::IN_SRAM_SIZE_CH_SPEC>;
153#[doc = "Receive L2 FIFO depth of Rx channel 0"]
154pub mod in_sram_size_ch;
155#[doc = "OUT_SRAM_SIZE_CH (rw) register accessor: Transmit L2 FIFO depth of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_sram_size_ch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_sram_size_ch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_sram_size_ch`] module"]
156pub type OUT_SRAM_SIZE_CH = crate::Reg<out_sram_size_ch::OUT_SRAM_SIZE_CH_SPEC>;
157#[doc = "Transmit L2 FIFO depth of Tx channel 0"]
158pub mod out_sram_size_ch;
159#[doc = "EXTMEM_REJECT_ADDR (r) register accessor: Reject address accessing external RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`extmem_reject_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extmem_reject_addr`] module"]
160pub type EXTMEM_REJECT_ADDR = crate::Reg<extmem_reject_addr::EXTMEM_REJECT_ADDR_SPEC>;
161#[doc = "Reject address accessing external RAM"]
162pub mod extmem_reject_addr;
163#[doc = "EXTMEM_REJECT_ST (r) register accessor: Reject status accessing external RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`extmem_reject_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extmem_reject_st`] module"]
164pub type EXTMEM_REJECT_ST = crate::Reg<extmem_reject_st::EXTMEM_REJECT_ST_SPEC>;
165#[doc = "Reject status accessing external RAM"]
166pub mod extmem_reject_st;
167#[doc = "EXTMEM_REJECT_INT_RAW (rw) register accessor: Raw interrupt status of external RAM permission\n\nYou can [`read`](crate::Reg::read) this register and get [`extmem_reject_int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extmem_reject_int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extmem_reject_int_raw`] module"]
168pub type EXTMEM_REJECT_INT_RAW = crate::Reg<extmem_reject_int_raw::EXTMEM_REJECT_INT_RAW_SPEC>;
169#[doc = "Raw interrupt status of external RAM permission"]
170pub mod extmem_reject_int_raw;
171#[doc = "EXTMEM_REJECT_INT_ST (r) register accessor: Masked interrupt status of external RAM permission\n\nYou can [`read`](crate::Reg::read) this register and get [`extmem_reject_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extmem_reject_int_st`] module"]
172pub type EXTMEM_REJECT_INT_ST = crate::Reg<extmem_reject_int_st::EXTMEM_REJECT_INT_ST_SPEC>;
173#[doc = "Masked interrupt status of external RAM permission"]
174pub mod extmem_reject_int_st;
175#[doc = "EXTMEM_REJECT_INT_ENA (rw) register accessor: Interrupt enable bits of external RAM permission\n\nYou can [`read`](crate::Reg::read) this register and get [`extmem_reject_int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extmem_reject_int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extmem_reject_int_ena`] module"]
176pub type EXTMEM_REJECT_INT_ENA = crate::Reg<extmem_reject_int_ena::EXTMEM_REJECT_INT_ENA_SPEC>;
177#[doc = "Interrupt enable bits of external RAM permission"]
178pub mod extmem_reject_int_ena;
179#[doc = "EXTMEM_REJECT_INT_CLR (w) register accessor: Interrupt clear bits of external RAM permission\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extmem_reject_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@extmem_reject_int_clr`] module"]
180pub type EXTMEM_REJECT_INT_CLR = crate::Reg<extmem_reject_int_clr::EXTMEM_REJECT_INT_CLR_SPEC>;
181#[doc = "Interrupt clear bits of external RAM permission"]
182pub mod extmem_reject_int_clr;
183#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
184pub type DATE = crate::Reg<date::DATE_SPEC>;
185#[doc = "Version control register"]
186pub mod date;