1#[doc = "Register `MISC` reader"]
2pub type R = crate::R<MISC_SPEC>;
3#[doc = "Register `MISC` writer"]
4pub type W = crate::W<MISC_SPEC>;
5#[doc = "Field `CS0_DIS` reader - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
6pub type CS0_DIS_R = crate::BitReader;
7#[doc = "Field `CS0_DIS` writer - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
8pub type CS0_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CS1_DIS` reader - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
10pub type CS1_DIS_R = crate::BitReader;
11#[doc = "Field `CS1_DIS` writer - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
12pub type CS1_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CS2_DIS` reader - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
14pub type CS2_DIS_R = crate::BitReader;
15#[doc = "Field `CS2_DIS` writer - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
16pub type CS2_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CS3_DIS` reader - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."]
18pub type CS3_DIS_R = crate::BitReader;
19#[doc = "Field `CS3_DIS` writer - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."]
20pub type CS3_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CS4_DIS` reader - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."]
22pub type CS4_DIS_R = crate::BitReader;
23#[doc = "Field `CS4_DIS` writer - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."]
24pub type CS4_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CS5_DIS` reader - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."]
26pub type CS5_DIS_R = crate::BitReader;
27#[doc = "Field `CS5_DIS` writer - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."]
28pub type CS5_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CK_DIS` reader - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
30pub type CK_DIS_R = crate::BitReader;
31#[doc = "Field `CK_DIS` writer - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
32pub type CK_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `MASTER_CS_POL` reader - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
34pub type MASTER_CS_POL_R = crate::FieldReader;
35#[doc = "Field `MASTER_CS_POL` writer - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
36pub type MASTER_CS_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
37#[doc = "Field `CLK_DATA_DTR_EN` reader - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."]
38pub type CLK_DATA_DTR_EN_R = crate::BitReader;
39#[doc = "Field `CLK_DATA_DTR_EN` writer - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."]
40pub type CLK_DATA_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `DATA_DTR_EN` reader - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."]
42pub type DATA_DTR_EN_R = crate::BitReader;
43#[doc = "Field `DATA_DTR_EN` writer - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."]
44pub type DATA_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `ADDR_DTR_EN` reader - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."]
46pub type ADDR_DTR_EN_R = crate::BitReader;
47#[doc = "Field `ADDR_DTR_EN` writer - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."]
48pub type ADDR_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CMD_DTR_EN` reader - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."]
50pub type CMD_DTR_EN_R = crate::BitReader;
51#[doc = "Field `CMD_DTR_EN` writer - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."]
52pub type CMD_DTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `SLAVE_CS_POL` reader - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
54pub type SLAVE_CS_POL_R = crate::BitReader;
55#[doc = "Field `SLAVE_CS_POL` writer - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
56pub type SLAVE_CS_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `DQS_IDLE_EDGE` reader - The default value of spi_dqs. Can be configured in CONF state."]
58pub type DQS_IDLE_EDGE_R = crate::BitReader;
59#[doc = "Field `DQS_IDLE_EDGE` writer - The default value of spi_dqs. Can be configured in CONF state."]
60pub type DQS_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `CK_IDLE_EDGE` reader - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
62pub type CK_IDLE_EDGE_R = crate::BitReader;
63#[doc = "Field `CK_IDLE_EDGE` writer - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
64pub type CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `CS_KEEP_ACTIVE` reader - spi cs line keep low when the bit is set. Can be configured in CONF state."]
66pub type CS_KEEP_ACTIVE_R = crate::BitReader;
67#[doc = "Field `CS_KEEP_ACTIVE` writer - spi cs line keep low when the bit is set. Can be configured in CONF state."]
68pub type CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `QUAD_DIN_PIN_SWAP` reader - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state."]
70pub type QUAD_DIN_PIN_SWAP_R = crate::BitReader;
71#[doc = "Field `QUAD_DIN_PIN_SWAP` writer - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state."]
72pub type QUAD_DIN_PIN_SWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
73impl R {
74 #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
75 #[inline(always)]
76 pub fn cs0_dis(&self) -> CS0_DIS_R {
77 CS0_DIS_R::new((self.bits & 1) != 0)
78 }
79 #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
80 #[inline(always)]
81 pub fn cs1_dis(&self) -> CS1_DIS_R {
82 CS1_DIS_R::new(((self.bits >> 1) & 1) != 0)
83 }
84 #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
85 #[inline(always)]
86 pub fn cs2_dis(&self) -> CS2_DIS_R {
87 CS2_DIS_R::new(((self.bits >> 2) & 1) != 0)
88 }
89 #[doc = "Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."]
90 #[inline(always)]
91 pub fn cs3_dis(&self) -> CS3_DIS_R {
92 CS3_DIS_R::new(((self.bits >> 3) & 1) != 0)
93 }
94 #[doc = "Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."]
95 #[inline(always)]
96 pub fn cs4_dis(&self) -> CS4_DIS_R {
97 CS4_DIS_R::new(((self.bits >> 4) & 1) != 0)
98 }
99 #[doc = "Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."]
100 #[inline(always)]
101 pub fn cs5_dis(&self) -> CS5_DIS_R {
102 CS5_DIS_R::new(((self.bits >> 5) & 1) != 0)
103 }
104 #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
105 #[inline(always)]
106 pub fn ck_dis(&self) -> CK_DIS_R {
107 CK_DIS_R::new(((self.bits >> 6) & 1) != 0)
108 }
109 #[doc = "Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
110 #[inline(always)]
111 pub fn master_cs_pol(&self) -> MASTER_CS_POL_R {
112 MASTER_CS_POL_R::new(((self.bits >> 7) & 0x3f) as u8)
113 }
114 #[doc = "Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."]
115 #[inline(always)]
116 pub fn clk_data_dtr_en(&self) -> CLK_DATA_DTR_EN_R {
117 CLK_DATA_DTR_EN_R::new(((self.bits >> 16) & 1) != 0)
118 }
119 #[doc = "Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."]
120 #[inline(always)]
121 pub fn data_dtr_en(&self) -> DATA_DTR_EN_R {
122 DATA_DTR_EN_R::new(((self.bits >> 17) & 1) != 0)
123 }
124 #[doc = "Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."]
125 #[inline(always)]
126 pub fn addr_dtr_en(&self) -> ADDR_DTR_EN_R {
127 ADDR_DTR_EN_R::new(((self.bits >> 18) & 1) != 0)
128 }
129 #[doc = "Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."]
130 #[inline(always)]
131 pub fn cmd_dtr_en(&self) -> CMD_DTR_EN_R {
132 CMD_DTR_EN_R::new(((self.bits >> 19) & 1) != 0)
133 }
134 #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
135 #[inline(always)]
136 pub fn slave_cs_pol(&self) -> SLAVE_CS_POL_R {
137 SLAVE_CS_POL_R::new(((self.bits >> 23) & 1) != 0)
138 }
139 #[doc = "Bit 24 - The default value of spi_dqs. Can be configured in CONF state."]
140 #[inline(always)]
141 pub fn dqs_idle_edge(&self) -> DQS_IDLE_EDGE_R {
142 DQS_IDLE_EDGE_R::new(((self.bits >> 24) & 1) != 0)
143 }
144 #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
145 #[inline(always)]
146 pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R {
147 CK_IDLE_EDGE_R::new(((self.bits >> 29) & 1) != 0)
148 }
149 #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."]
150 #[inline(always)]
151 pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R {
152 CS_KEEP_ACTIVE_R::new(((self.bits >> 30) & 1) != 0)
153 }
154 #[doc = "Bit 31 - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state."]
155 #[inline(always)]
156 pub fn quad_din_pin_swap(&self) -> QUAD_DIN_PIN_SWAP_R {
157 QUAD_DIN_PIN_SWAP_R::new(((self.bits >> 31) & 1) != 0)
158 }
159}
160#[cfg(feature = "impl-register-debug")]
161impl core::fmt::Debug for R {
162 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
163 f.debug_struct("MISC")
164 .field("cs0_dis", &self.cs0_dis())
165 .field("cs1_dis", &self.cs1_dis())
166 .field("cs2_dis", &self.cs2_dis())
167 .field("cs3_dis", &self.cs3_dis())
168 .field("cs4_dis", &self.cs4_dis())
169 .field("cs5_dis", &self.cs5_dis())
170 .field("ck_dis", &self.ck_dis())
171 .field("master_cs_pol", &self.master_cs_pol())
172 .field("clk_data_dtr_en", &self.clk_data_dtr_en())
173 .field("data_dtr_en", &self.data_dtr_en())
174 .field("addr_dtr_en", &self.addr_dtr_en())
175 .field("cmd_dtr_en", &self.cmd_dtr_en())
176 .field("slave_cs_pol", &self.slave_cs_pol())
177 .field("dqs_idle_edge", &self.dqs_idle_edge())
178 .field("ck_idle_edge", &self.ck_idle_edge())
179 .field("cs_keep_active", &self.cs_keep_active())
180 .field("quad_din_pin_swap", &self.quad_din_pin_swap())
181 .finish()
182 }
183}
184impl W {
185 #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
186 #[inline(always)]
187 pub fn cs0_dis(&mut self) -> CS0_DIS_W<MISC_SPEC> {
188 CS0_DIS_W::new(self, 0)
189 }
190 #[doc = "Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state."]
191 #[inline(always)]
192 pub fn cs1_dis(&mut self) -> CS1_DIS_W<MISC_SPEC> {
193 CS1_DIS_W::new(self, 1)
194 }
195 #[doc = "Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state."]
196 #[inline(always)]
197 pub fn cs2_dis(&mut self) -> CS2_DIS_W<MISC_SPEC> {
198 CS2_DIS_W::new(self, 2)
199 }
200 #[doc = "Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state."]
201 #[inline(always)]
202 pub fn cs3_dis(&mut self) -> CS3_DIS_W<MISC_SPEC> {
203 CS3_DIS_W::new(self, 3)
204 }
205 #[doc = "Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state."]
206 #[inline(always)]
207 pub fn cs4_dis(&mut self) -> CS4_DIS_W<MISC_SPEC> {
208 CS4_DIS_W::new(self, 4)
209 }
210 #[doc = "Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state."]
211 #[inline(always)]
212 pub fn cs5_dis(&mut self) -> CS5_DIS_W<MISC_SPEC> {
213 CS5_DIS_W::new(self, 5)
214 }
215 #[doc = "Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state."]
216 #[inline(always)]
217 pub fn ck_dis(&mut self) -> CK_DIS_W<MISC_SPEC> {
218 CK_DIS_W::new(self, 6)
219 }
220 #[doc = "Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state."]
221 #[inline(always)]
222 pub fn master_cs_pol(&mut self) -> MASTER_CS_POL_W<MISC_SPEC> {
223 MASTER_CS_POL_W::new(self, 7)
224 }
225 #[doc = "Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19."]
226 #[inline(always)]
227 pub fn clk_data_dtr_en(&mut self) -> CLK_DATA_DTR_EN_W<MISC_SPEC> {
228 CLK_DATA_DTR_EN_W::new(self, 16)
229 }
230 #[doc = "Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state."]
231 #[inline(always)]
232 pub fn data_dtr_en(&mut self) -> DATA_DTR_EN_W<MISC_SPEC> {
233 DATA_DTR_EN_W::new(self, 17)
234 }
235 #[doc = "Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state."]
236 #[inline(always)]
237 pub fn addr_dtr_en(&mut self) -> ADDR_DTR_EN_W<MISC_SPEC> {
238 ADDR_DTR_EN_W::new(self, 18)
239 }
240 #[doc = "Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state."]
241 #[inline(always)]
242 pub fn cmd_dtr_en(&mut self) -> CMD_DTR_EN_W<MISC_SPEC> {
243 CMD_DTR_EN_W::new(self, 19)
244 }
245 #[doc = "Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state."]
246 #[inline(always)]
247 pub fn slave_cs_pol(&mut self) -> SLAVE_CS_POL_W<MISC_SPEC> {
248 SLAVE_CS_POL_W::new(self, 23)
249 }
250 #[doc = "Bit 24 - The default value of spi_dqs. Can be configured in CONF state."]
251 #[inline(always)]
252 pub fn dqs_idle_edge(&mut self) -> DQS_IDLE_EDGE_W<MISC_SPEC> {
253 DQS_IDLE_EDGE_W::new(self, 24)
254 }
255 #[doc = "Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state."]
256 #[inline(always)]
257 pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
258 CK_IDLE_EDGE_W::new(self, 29)
259 }
260 #[doc = "Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state."]
261 #[inline(always)]
262 pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
263 CS_KEEP_ACTIVE_W::new(self, 30)
264 }
265 #[doc = "Bit 31 - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state."]
266 #[inline(always)]
267 pub fn quad_din_pin_swap(&mut self) -> QUAD_DIN_PIN_SWAP_W<MISC_SPEC> {
268 QUAD_DIN_PIN_SWAP_W::new(self, 31)
269 }
270}
271#[doc = "SPI misc register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
272pub struct MISC_SPEC;
273impl crate::RegisterSpec for MISC_SPEC {
274 type Ux = u32;
275}
276#[doc = "`read()` method returns [`misc::R`](R) reader structure"]
277impl crate::Readable for MISC_SPEC {}
278#[doc = "`write(|w| ..)` method takes [`misc::W`](W) writer structure"]
279impl crate::Writable for MISC_SPEC {
280 type Safety = crate::Unsafe;
281}
282#[doc = "`reset()` method sets MISC to value 0x3e"]
283impl crate::Resettable for MISC_SPEC {
284 const RESET_VALUE: u32 = 0x3e;
285}