Struct esp32s3::spi2::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 38 fields
    pub cmd: CMD,
    pub addr: ADDR,
    pub ctrl: CTRL,
    pub clock: CLOCK,
    pub user: USER,
    pub user1: USER1,
    pub user2: USER2,
    pub ms_dlen: MS_DLEN,
    pub misc: MISC,
    pub din_mode: DIN_MODE,
    pub din_num: DIN_NUM,
    pub dout_mode: DOUT_MODE,
    pub dma_conf: DMA_CONF,
    pub dma_int_ena: DMA_INT_ENA,
    pub dma_int_clr: DMA_INT_CLR,
    pub dma_int_raw: DMA_INT_RAW,
    pub dma_int_st: DMA_INT_ST,
    pub dma_int_set: DMA_INT_SET,
    pub w0: W0,
    pub w1: W1,
    pub w2: W2,
    pub w3: W3,
    pub w4: W4,
    pub w5: W5,
    pub w6: W6,
    pub w7: W7,
    pub w8: W8,
    pub w9: W9,
    pub w10: W10,
    pub w11: W11,
    pub w12: W12,
    pub w13: W13,
    pub w14: W14,
    pub w15: W15,
    pub slave: SLAVE,
    pub slave1: SLAVE1,
    pub clk_gate: CLK_GATE,
    pub date: DATE,
    /* private fields */

}
Expand description

Register block

Fields§

§cmd: CMD

0x00 - Command control register

§addr: ADDR

0x04 - Address value register

§ctrl: CTRL

0x08 - SPI control register

§clock: CLOCK

0x0c - SPI clock control register

§user: USER

0x10 - SPI USER control register

§user1: USER1

0x14 - SPI USER control register 1

§user2: USER2

0x18 - SPI USER control register 2

§ms_dlen: MS_DLEN

0x1c - SPI data bit length control register

§misc: MISC

0x20 - SPI misc register

§din_mode: DIN_MODE

0x24 - SPI input delay mode configuration

§din_num: DIN_NUM

0x28 - SPI input delay number configuration

§dout_mode: DOUT_MODE

0x2c - SPI output delay mode configuration

§dma_conf: DMA_CONF

0x30 - SPI DMA control register

§dma_int_ena: DMA_INT_ENA

0x34 - SPI interrupt enable register

§dma_int_clr: DMA_INT_CLR

0x38 - SPI interrupt clear register

§dma_int_raw: DMA_INT_RAW

0x3c - SPI interrupt raw register

§dma_int_st: DMA_INT_ST

0x40 - SPI interrupt status register

§dma_int_set: DMA_INT_SET

0x44 - SPI interrupt software set register

§w0: W0

0x98 - SPI CPU-controlled buffer0

§w1: W1

0x9c - SPI CPU-controlled buffer1

§w2: W2

0xa0 - SPI CPU-controlled buffer2

§w3: W3

0xa4 - SPI CPU-controlled buffer3

§w4: W4

0xa8 - SPI CPU-controlled buffer4

§w5: W5

0xac - SPI CPU-controlled buffer5

§w6: W6

0xb0 - SPI CPU-controlled buffer6

§w7: W7

0xb4 - SPI CPU-controlled buffer7

§w8: W8

0xb8 - SPI CPU-controlled buffer8

§w9: W9

0xbc - SPI CPU-controlled buffer9

§w10: W10

0xc0 - SPI CPU-controlled buffer10

§w11: W11

0xc4 - SPI CPU-controlled buffer11

§w12: W12

0xc8 - SPI CPU-controlled buffer12

§w13: W13

0xcc - SPI CPU-controlled buffer13

§w14: W14

0xd0 - SPI CPU-controlled buffer14

§w15: W15

0xd4 - SPI CPU-controlled buffer15

§slave: SLAVE

0xe0 - SPI slave control register

§slave1: SLAVE1

0xe4 - SPI slave control register 1

§clk_gate: CLK_GATE

0xe8 - SPI module clock and register clock control

§date: DATE

0xf0 - Version control

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