esp32s3 0.35.0

Peripheral access crate for the ESP32-S3
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

#[doc = "Register `PMS_CONSTRAIN_1` reader"]
pub type R = crate::R<PMS_CONSTRAIN_1_SPEC>;
#[doc = "Register `PMS_CONSTRAIN_1` writer"]
pub type W = crate::W<PMS_CONSTRAIN_1_SPEC>;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0` reader - spi2's permission(store,load) in data region0 of SRAM"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_R = crate::FieldReader;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0` writer - spi2's permission(store,load) in data region0 of SRAM"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1` reader - spi2's permission(store,load) in data region1 of SRAM"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_R = crate::FieldReader;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1` writer - spi2's permission(store,load) in data region1 of SRAM"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2` reader - spi2's permission(store,load) in data region2 of SRAM"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_R = crate::FieldReader;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2` writer - spi2's permission(store,load) in data region2 of SRAM"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3` reader - spi2's permission(store,load) in data region3 of SRAM"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_R = crate::FieldReader;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3` writer - spi2's permission(store,load) in data region3 of SRAM"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0` reader - spi2's permission(store,load) in dcache data sram block0"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_R = crate::FieldReader;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0` writer - spi2's permission(store,load) in dcache data sram block0"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<'a, REG> =
    crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1` reader - spi2's permission(store,load) in dcache data sram block1"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_R = crate::FieldReader;
#[doc = "Field `DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1` writer - spi2's permission(store,load) in dcache data sram block1"]
pub type DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<'a, REG> =
    crate::FieldWriter<'a, REG, 2>;
impl R {
    #[doc = "Bits 0:1 - spi2's permission(store,load) in data region0 of SRAM"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_pms_0(
        &self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_R {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_R::new((self.bits & 3) as u8)
    }
    #[doc = "Bits 2:3 - spi2's permission(store,load) in data region1 of SRAM"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_pms_1(
        &self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_R {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_R::new(((self.bits >> 2) & 3) as u8)
    }
    #[doc = "Bits 4:5 - spi2's permission(store,load) in data region2 of SRAM"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_pms_2(
        &self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_R {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_R::new(((self.bits >> 4) & 3) as u8)
    }
    #[doc = "Bits 6:7 - spi2's permission(store,load) in data region3 of SRAM"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_pms_3(
        &self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_R {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_R::new(((self.bits >> 6) & 3) as u8)
    }
    #[doc = "Bits 8:9 - spi2's permission(store,load) in dcache data sram block0"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0(
        &self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_R {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_R::new(
            ((self.bits >> 8) & 3) as u8,
        )
    }
    #[doc = "Bits 10:11 - spi2's permission(store,load) in dcache data sram block1"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1(
        &self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_R {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_R::new(
            ((self.bits >> 10) & 3) as u8,
        )
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PMS_CONSTRAIN_1")
            .field(
                "dma_apbperi_spi2_pms_constrain_sram_pms_0",
                &self.dma_apbperi_spi2_pms_constrain_sram_pms_0(),
            )
            .field(
                "dma_apbperi_spi2_pms_constrain_sram_pms_1",
                &self.dma_apbperi_spi2_pms_constrain_sram_pms_1(),
            )
            .field(
                "dma_apbperi_spi2_pms_constrain_sram_pms_2",
                &self.dma_apbperi_spi2_pms_constrain_sram_pms_2(),
            )
            .field(
                "dma_apbperi_spi2_pms_constrain_sram_pms_3",
                &self.dma_apbperi_spi2_pms_constrain_sram_pms_3(),
            )
            .field(
                "dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0",
                &self.dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0(),
            )
            .field(
                "dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1",
                &self.dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1(),
            )
            .finish()
    }
}
impl W {
    #[doc = "Bits 0:1 - spi2's permission(store,load) in data region0 of SRAM"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_pms_0(
        &mut self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_W<'_, PMS_CONSTRAIN_1_SPEC> {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_W::new(self, 0)
    }
    #[doc = "Bits 2:3 - spi2's permission(store,load) in data region1 of SRAM"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_pms_1(
        &mut self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_W<'_, PMS_CONSTRAIN_1_SPEC> {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_W::new(self, 2)
    }
    #[doc = "Bits 4:5 - spi2's permission(store,load) in data region2 of SRAM"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_pms_2(
        &mut self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_W<'_, PMS_CONSTRAIN_1_SPEC> {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_W::new(self, 4)
    }
    #[doc = "Bits 6:7 - spi2's permission(store,load) in data region3 of SRAM"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_pms_3(
        &mut self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_W<'_, PMS_CONSTRAIN_1_SPEC> {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_W::new(self, 6)
    }
    #[doc = "Bits 8:9 - spi2's permission(store,load) in dcache data sram block0"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0(
        &mut self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W<'_, PMS_CONSTRAIN_1_SPEC> {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_W::new(self, 8)
    }
    #[doc = "Bits 10:11 - spi2's permission(store,load) in dcache data sram block1"]
    #[inline(always)]
    pub fn dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1(
        &mut self,
    ) -> DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W<'_, PMS_CONSTRAIN_1_SPEC> {
        DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_W::new(self, 10)
    }
}
#[doc = "spi2 dma permission configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`pms_constrain_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pms_constrain_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PMS_CONSTRAIN_1_SPEC;
impl crate::RegisterSpec for PMS_CONSTRAIN_1_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`pms_constrain_1::R`](R) reader structure"]
impl crate::Readable for PMS_CONSTRAIN_1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`pms_constrain_1::W`](W) writer structure"]
impl crate::Writable for PMS_CONSTRAIN_1_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PMS_CONSTRAIN_1 to value 0x0fff"]
impl crate::Resettable for PMS_CONSTRAIN_1_SPEC {
    const RESET_VALUE: u32 = 0x0fff;
}