esp32s3 0.35.0

Peripheral access crate for the ESP32-S3
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172

#[doc = "Register `LCD_MISC` reader"]
pub type R = crate::R<LCD_MISC_SPEC>;
#[doc = "Register `LCD_MISC` writer"]
pub type W = crate::W<LCD_MISC_SPEC>;
#[doc = "Field `LCD_AFIFO_THRESHOLD_NUM` reader - Set the threshold for Async Tx FIFO full event."]
pub type LCD_AFIFO_THRESHOLD_NUM_R = crate::FieldReader;
#[doc = "Field `LCD_AFIFO_THRESHOLD_NUM` writer - Set the threshold for Async Tx FIFO full event."]
pub type LCD_AFIFO_THRESHOLD_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
#[doc = "Field `LCD_VFK_CYCLELEN` reader - Configure the setup cycles in LCD non-RGB mode. Setup cycles expected = this value + 1."]
pub type LCD_VFK_CYCLELEN_R = crate::FieldReader;
#[doc = "Field `LCD_VFK_CYCLELEN` writer - Configure the setup cycles in LCD non-RGB mode. Setup cycles expected = this value + 1."]
pub type LCD_VFK_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
#[doc = "Field `LCD_VBK_CYCLELEN` reader - Configure the hold time cycles in LCD non-RGB mode. Hold cycles expected = this value + 1. %Configure the cycles for vertical back blank region in LCD RGB mode, the cycles = this value + 1. Or configure the hold time cycles in LCD non-RGB mode, the cycles = this value + 1."]
pub type LCD_VBK_CYCLELEN_R = crate::FieldReader<u16>;
#[doc = "Field `LCD_VBK_CYCLELEN` writer - Configure the hold time cycles in LCD non-RGB mode. Hold cycles expected = this value + 1. %Configure the cycles for vertical back blank region in LCD RGB mode, the cycles = this value + 1. Or configure the hold time cycles in LCD non-RGB mode, the cycles = this value + 1."]
pub type LCD_VBK_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
#[doc = "Field `LCD_NEXT_FRAME_EN` reader - 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out."]
pub type LCD_NEXT_FRAME_EN_R = crate::BitReader;
#[doc = "Field `LCD_NEXT_FRAME_EN` writer - 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out."]
pub type LCD_NEXT_FRAME_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LCD_BK_EN` reader - 1: Enable blank region when LCD sends data out. 0: No blank region."]
pub type LCD_BK_EN_R = crate::BitReader;
#[doc = "Field `LCD_BK_EN` writer - 1: Enable blank region when LCD sends data out. 0: No blank region."]
pub type LCD_BK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LCD_AFIFO_RESET` writer - Async Tx FIFO reset signal."]
pub type LCD_AFIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LCD_CD_DATA_SET` reader - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DOUT phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
pub type LCD_CD_DATA_SET_R = crate::BitReader;
#[doc = "Field `LCD_CD_DATA_SET` writer - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DOUT phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
pub type LCD_CD_DATA_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LCD_CD_DUMMY_SET` reader - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DUMMY phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
pub type LCD_CD_DUMMY_SET_R = crate::BitReader;
#[doc = "Field `LCD_CD_DUMMY_SET` writer - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DUMMY phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
pub type LCD_CD_DUMMY_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LCD_CD_CMD_SET` reader - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in CMD phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
pub type LCD_CD_CMD_SET_R = crate::BitReader;
#[doc = "Field `LCD_CD_CMD_SET` writer - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in CMD phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
pub type LCD_CD_CMD_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `LCD_CD_IDLE_EDGE` reader - The default value of LCD_CD."]
pub type LCD_CD_IDLE_EDGE_R = crate::BitReader;
#[doc = "Field `LCD_CD_IDLE_EDGE` writer - The default value of LCD_CD."]
pub type LCD_CD_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bits 1:5 - Set the threshold for Async Tx FIFO full event."]
    #[inline(always)]
    pub fn lcd_afifo_threshold_num(&self) -> LCD_AFIFO_THRESHOLD_NUM_R {
        LCD_AFIFO_THRESHOLD_NUM_R::new(((self.bits >> 1) & 0x1f) as u8)
    }
    #[doc = "Bits 6:11 - Configure the setup cycles in LCD non-RGB mode. Setup cycles expected = this value + 1."]
    #[inline(always)]
    pub fn lcd_vfk_cyclelen(&self) -> LCD_VFK_CYCLELEN_R {
        LCD_VFK_CYCLELEN_R::new(((self.bits >> 6) & 0x3f) as u8)
    }
    #[doc = "Bits 12:24 - Configure the hold time cycles in LCD non-RGB mode. Hold cycles expected = this value + 1. %Configure the cycles for vertical back blank region in LCD RGB mode, the cycles = this value + 1. Or configure the hold time cycles in LCD non-RGB mode, the cycles = this value + 1."]
    #[inline(always)]
    pub fn lcd_vbk_cyclelen(&self) -> LCD_VBK_CYCLELEN_R {
        LCD_VBK_CYCLELEN_R::new(((self.bits >> 12) & 0x1fff) as u16)
    }
    #[doc = "Bit 25 - 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out."]
    #[inline(always)]
    pub fn lcd_next_frame_en(&self) -> LCD_NEXT_FRAME_EN_R {
        LCD_NEXT_FRAME_EN_R::new(((self.bits >> 25) & 1) != 0)
    }
    #[doc = "Bit 26 - 1: Enable blank region when LCD sends data out. 0: No blank region."]
    #[inline(always)]
    pub fn lcd_bk_en(&self) -> LCD_BK_EN_R {
        LCD_BK_EN_R::new(((self.bits >> 26) & 1) != 0)
    }
    #[doc = "Bit 28 - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DOUT phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
    #[inline(always)]
    pub fn lcd_cd_data_set(&self) -> LCD_CD_DATA_SET_R {
        LCD_CD_DATA_SET_R::new(((self.bits >> 28) & 1) != 0)
    }
    #[doc = "Bit 29 - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DUMMY phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
    #[inline(always)]
    pub fn lcd_cd_dummy_set(&self) -> LCD_CD_DUMMY_SET_R {
        LCD_CD_DUMMY_SET_R::new(((self.bits >> 29) & 1) != 0)
    }
    #[doc = "Bit 30 - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in CMD phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
    #[inline(always)]
    pub fn lcd_cd_cmd_set(&self) -> LCD_CD_CMD_SET_R {
        LCD_CD_CMD_SET_R::new(((self.bits >> 30) & 1) != 0)
    }
    #[doc = "Bit 31 - The default value of LCD_CD."]
    #[inline(always)]
    pub fn lcd_cd_idle_edge(&self) -> LCD_CD_IDLE_EDGE_R {
        LCD_CD_IDLE_EDGE_R::new(((self.bits >> 31) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LCD_MISC")
            .field("lcd_afifo_threshold_num", &self.lcd_afifo_threshold_num())
            .field("lcd_vfk_cyclelen", &self.lcd_vfk_cyclelen())
            .field("lcd_vbk_cyclelen", &self.lcd_vbk_cyclelen())
            .field("lcd_next_frame_en", &self.lcd_next_frame_en())
            .field("lcd_bk_en", &self.lcd_bk_en())
            .field("lcd_cd_data_set", &self.lcd_cd_data_set())
            .field("lcd_cd_dummy_set", &self.lcd_cd_dummy_set())
            .field("lcd_cd_cmd_set", &self.lcd_cd_cmd_set())
            .field("lcd_cd_idle_edge", &self.lcd_cd_idle_edge())
            .finish()
    }
}
impl W {
    #[doc = "Bits 1:5 - Set the threshold for Async Tx FIFO full event."]
    #[inline(always)]
    pub fn lcd_afifo_threshold_num(&mut self) -> LCD_AFIFO_THRESHOLD_NUM_W<'_, LCD_MISC_SPEC> {
        LCD_AFIFO_THRESHOLD_NUM_W::new(self, 1)
    }
    #[doc = "Bits 6:11 - Configure the setup cycles in LCD non-RGB mode. Setup cycles expected = this value + 1."]
    #[inline(always)]
    pub fn lcd_vfk_cyclelen(&mut self) -> LCD_VFK_CYCLELEN_W<'_, LCD_MISC_SPEC> {
        LCD_VFK_CYCLELEN_W::new(self, 6)
    }
    #[doc = "Bits 12:24 - Configure the hold time cycles in LCD non-RGB mode. Hold cycles expected = this value + 1. %Configure the cycles for vertical back blank region in LCD RGB mode, the cycles = this value + 1. Or configure the hold time cycles in LCD non-RGB mode, the cycles = this value + 1."]
    #[inline(always)]
    pub fn lcd_vbk_cyclelen(&mut self) -> LCD_VBK_CYCLELEN_W<'_, LCD_MISC_SPEC> {
        LCD_VBK_CYCLELEN_W::new(self, 12)
    }
    #[doc = "Bit 25 - 1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out."]
    #[inline(always)]
    pub fn lcd_next_frame_en(&mut self) -> LCD_NEXT_FRAME_EN_W<'_, LCD_MISC_SPEC> {
        LCD_NEXT_FRAME_EN_W::new(self, 25)
    }
    #[doc = "Bit 26 - 1: Enable blank region when LCD sends data out. 0: No blank region."]
    #[inline(always)]
    pub fn lcd_bk_en(&mut self) -> LCD_BK_EN_W<'_, LCD_MISC_SPEC> {
        LCD_BK_EN_W::new(self, 26)
    }
    #[doc = "Bit 27 - Async Tx FIFO reset signal."]
    #[inline(always)]
    pub fn lcd_afifo_reset(&mut self) -> LCD_AFIFO_RESET_W<'_, LCD_MISC_SPEC> {
        LCD_AFIFO_RESET_W::new(self, 27)
    }
    #[doc = "Bit 28 - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DOUT phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
    #[inline(always)]
    pub fn lcd_cd_data_set(&mut self) -> LCD_CD_DATA_SET_W<'_, LCD_MISC_SPEC> {
        LCD_CD_DATA_SET_W::new(self, 28)
    }
    #[doc = "Bit 29 - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DUMMY phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
    #[inline(always)]
    pub fn lcd_cd_dummy_set(&mut self) -> LCD_CD_DUMMY_SET_W<'_, LCD_MISC_SPEC> {
        LCD_CD_DUMMY_SET_W::new(self, 29)
    }
    #[doc = "Bit 30 - 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in CMD phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE."]
    #[inline(always)]
    pub fn lcd_cd_cmd_set(&mut self) -> LCD_CD_CMD_SET_W<'_, LCD_MISC_SPEC> {
        LCD_CD_CMD_SET_W::new(self, 30)
    }
    #[doc = "Bit 31 - The default value of LCD_CD."]
    #[inline(always)]
    pub fn lcd_cd_idle_edge(&mut self) -> LCD_CD_IDLE_EDGE_W<'_, LCD_MISC_SPEC> {
        LCD_CD_IDLE_EDGE_W::new(self, 31)
    }
}
#[doc = "LCD MISC configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LCD_MISC_SPEC;
impl crate::RegisterSpec for LCD_MISC_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`lcd_misc::R`](R) reader structure"]
impl crate::Readable for LCD_MISC_SPEC {}
#[doc = "`write(|w| ..)` method takes [`lcd_misc::W`](W) writer structure"]
impl crate::Writable for LCD_MISC_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets LCD_MISC to value 0x22"]
impl crate::Resettable for LCD_MISC_SPEC {
    const RESET_VALUE: u32 = 0x22;
}