1#[doc = "Register `MISC` reader"]
2pub type R = crate::R<MISC_SPEC>;
3#[doc = "Register `MISC` writer"]
4pub type W = crate::W<MISC_SPEC>;
5#[doc = "Field `CS_DIS(0-1)` reader - Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"]
6pub type CS_DIS_R = crate::BitReader;
7#[doc = "Field `CS_DIS(0-1)` writer - Set this bit to raise high SPI_CS%s pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS%s is in low level when SPI1 transfer starts"]
8pub type CS_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FSUB_PIN` reader - Flash is connected to SPI SUBPIN bus."]
10pub type FSUB_PIN_R = crate::BitReader;
11#[doc = "Field `FSUB_PIN` writer - Flash is connected to SPI SUBPIN bus."]
12pub type FSUB_PIN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SSUB_PIN` reader - Ext_RAM is connected to SPI SUBPIN bus."]
14pub type SSUB_PIN_R = crate::BitReader;
15#[doc = "Field `SSUB_PIN` writer - Ext_RAM is connected to SPI SUBPIN bus."]
16pub type SSUB_PIN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CK_IDLE_EDGE` reader - 1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle"]
18pub type CK_IDLE_EDGE_R = crate::BitReader;
19#[doc = "Field `CK_IDLE_EDGE` writer - 1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle"]
20pub type CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CS_KEEP_ACTIVE` reader - SPI_CS line keep low when the bit is set."]
22pub type CS_KEEP_ACTIVE_R = crate::BitReader;
23#[doc = "Field `CS_KEEP_ACTIVE` writer - SPI_CS line keep low when the bit is set."]
24pub type CS_KEEP_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26 #[doc = "Set this bit to raise high SPI_CS(0-1) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-1) is in low level when SPI1 transfer starts"]
27 #[doc = ""]
28 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
29 #[inline(always)]
30 pub fn cs_dis(&self, n: u8) -> CS_DIS_R {
31 #[allow(clippy::no_effect)]
32 [(); 2][n as usize];
33 CS_DIS_R::new(((self.bits >> n) & 1) != 0)
34 }
35 #[doc = "Iterator for array of:"]
36 #[doc = "Set this bit to raise high SPI_CS(0-1) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-1) is in low level when SPI1 transfer starts"]
37 #[inline(always)]
38 pub fn cs_dis_iter(&self) -> impl Iterator<Item = CS_DIS_R> + '_ {
39 (0..2).map(move |n| CS_DIS_R::new(((self.bits >> n) & 1) != 0))
40 }
41 #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
42 #[inline(always)]
43 pub fn cs0_dis(&self) -> CS_DIS_R {
44 CS_DIS_R::new((self.bits & 1) != 0)
45 }
46 #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
47 #[inline(always)]
48 pub fn cs1_dis(&self) -> CS_DIS_R {
49 CS_DIS_R::new(((self.bits >> 1) & 1) != 0)
50 }
51 #[doc = "Bit 7 - Flash is connected to SPI SUBPIN bus."]
52 #[inline(always)]
53 pub fn fsub_pin(&self) -> FSUB_PIN_R {
54 FSUB_PIN_R::new(((self.bits >> 7) & 1) != 0)
55 }
56 #[doc = "Bit 8 - Ext_RAM is connected to SPI SUBPIN bus."]
57 #[inline(always)]
58 pub fn ssub_pin(&self) -> SSUB_PIN_R {
59 SSUB_PIN_R::new(((self.bits >> 8) & 1) != 0)
60 }
61 #[doc = "Bit 9 - 1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle"]
62 #[inline(always)]
63 pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R {
64 CK_IDLE_EDGE_R::new(((self.bits >> 9) & 1) != 0)
65 }
66 #[doc = "Bit 10 - SPI_CS line keep low when the bit is set."]
67 #[inline(always)]
68 pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R {
69 CS_KEEP_ACTIVE_R::new(((self.bits >> 10) & 1) != 0)
70 }
71}
72#[cfg(feature = "impl-register-debug")]
73impl core::fmt::Debug for R {
74 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
75 f.debug_struct("MISC")
76 .field("fsub_pin", &self.fsub_pin())
77 .field("ssub_pin", &self.ssub_pin())
78 .field("ck_idle_edge", &self.ck_idle_edge())
79 .field("cs_keep_active", &self.cs_keep_active())
80 .field("cs0_dis", &self.cs0_dis())
81 .field("cs1_dis", &self.cs1_dis())
82 .finish()
83 }
84}
85impl W {
86 #[doc = "Set this bit to raise high SPI_CS(0-1) pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS(0-1) is in low level when SPI1 transfer starts"]
87 #[doc = ""]
88 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CS0_DIS` field.</div>"]
89 #[inline(always)]
90 pub fn cs_dis(&mut self, n: u8) -> CS_DIS_W<MISC_SPEC> {
91 #[allow(clippy::no_effect)]
92 [(); 2][n as usize];
93 CS_DIS_W::new(self, n)
94 }
95 #[doc = "Bit 0 - Set this bit to raise high SPI_CS0 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS0 is in low level when SPI1 transfer starts"]
96 #[inline(always)]
97 pub fn cs0_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
98 CS_DIS_W::new(self, 0)
99 }
100 #[doc = "Bit 1 - Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM(0)/flash(1)) connected to SPI_CS1 is in low level when SPI1 transfer starts"]
101 #[inline(always)]
102 pub fn cs1_dis(&mut self) -> CS_DIS_W<MISC_SPEC> {
103 CS_DIS_W::new(self, 1)
104 }
105 #[doc = "Bit 7 - Flash is connected to SPI SUBPIN bus."]
106 #[inline(always)]
107 pub fn fsub_pin(&mut self) -> FSUB_PIN_W<MISC_SPEC> {
108 FSUB_PIN_W::new(self, 7)
109 }
110 #[doc = "Bit 8 - Ext_RAM is connected to SPI SUBPIN bus."]
111 #[inline(always)]
112 pub fn ssub_pin(&mut self) -> SSUB_PIN_W<MISC_SPEC> {
113 SSUB_PIN_W::new(self, 8)
114 }
115 #[doc = "Bit 9 - 1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle"]
116 #[inline(always)]
117 pub fn ck_idle_edge(&mut self) -> CK_IDLE_EDGE_W<MISC_SPEC> {
118 CK_IDLE_EDGE_W::new(self, 9)
119 }
120 #[doc = "Bit 10 - SPI_CS line keep low when the bit is set."]
121 #[inline(always)]
122 pub fn cs_keep_active(&mut self) -> CS_KEEP_ACTIVE_W<MISC_SPEC> {
123 CS_KEEP_ACTIVE_W::new(self, 10)
124 }
125}
126#[doc = "SPI0 misc register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
127pub struct MISC_SPEC;
128impl crate::RegisterSpec for MISC_SPEC {
129 type Ux = u32;
130}
131#[doc = "`read()` method returns [`misc::R`](R) reader structure"]
132impl crate::Readable for MISC_SPEC {}
133#[doc = "`write(|w| ..)` method takes [`misc::W`](W) writer structure"]
134impl crate::Writable for MISC_SPEC {
135 type Safety = crate::Unsafe;
136 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
137 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
138}
139#[doc = "`reset()` method sets MISC to value 0"]
140impl crate::Resettable for MISC_SPEC {
141 const RESET_VALUE: u32 = 0;
142}