1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `CONTROLLER_RESET` reader - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
6pub type CONTROLLER_RESET_R = crate::BitReader;
7#[doc = "Field `CONTROLLER_RESET` writer - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
8pub type CONTROLLER_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FIFO_RESET` reader - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."]
10pub type FIFO_RESET_R = crate::BitReader;
11#[doc = "Field `FIFO_RESET` writer - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."]
12pub type FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DMA_RESET` reader - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."]
14pub type DMA_RESET_R = crate::BitReader;
15#[doc = "Field `DMA_RESET` writer - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."]
16pub type DMA_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `INT_ENABLE` reader - Global interrupt enable/disable bit. 0: Disable; 1: Enable."]
18pub type INT_ENABLE_R = crate::BitReader;
19#[doc = "Field `INT_ENABLE` writer - Global interrupt enable/disable bit. 0: Disable; 1: Enable."]
20pub type INT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `READ_WAIT` reader - For sending read-wait to SDIO cards."]
22pub type READ_WAIT_R = crate::BitReader;
23#[doc = "Field `READ_WAIT` writer - For sending read-wait to SDIO cards."]
24pub type READ_WAIT_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SEND_IRQ_RESPONSE` reader - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."]
26pub type SEND_IRQ_RESPONSE_R = crate::BitReader;
27#[doc = "Field `SEND_IRQ_RESPONSE` writer - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."]
28pub type SEND_IRQ_RESPONSE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `ABORT_READ_DATA` reader - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."]
30pub type ABORT_READ_DATA_R = crate::BitReader;
31#[doc = "Field `ABORT_READ_DATA` writer - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."]
32pub type ABORT_READ_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SEND_CCSD` reader - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."]
34pub type SEND_CCSD_R = crate::BitReader;
35#[doc = "Field `SEND_CCSD` writer - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."]
36pub type SEND_CCSD_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SEND_AUTO_STOP_CCSD` reader - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."]
38pub type SEND_AUTO_STOP_CCSD_R = crate::BitReader;
39#[doc = "Field `SEND_AUTO_STOP_CCSD` writer - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."]
40pub type SEND_AUTO_STOP_CCSD_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CEATA_DEVICE_INTERRUPT_STATUS` reader - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."]
42pub type CEATA_DEVICE_INTERRUPT_STATUS_R = crate::BitReader;
43#[doc = "Field `CEATA_DEVICE_INTERRUPT_STATUS` writer - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."]
44pub type CEATA_DEVICE_INTERRUPT_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46 #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
47 #[inline(always)]
48 pub fn controller_reset(&self) -> CONTROLLER_RESET_R {
49 CONTROLLER_RESET_R::new((self.bits & 1) != 0)
50 }
51 #[doc = "Bit 1 - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."]
52 #[inline(always)]
53 pub fn fifo_reset(&self) -> FIFO_RESET_R {
54 FIFO_RESET_R::new(((self.bits >> 1) & 1) != 0)
55 }
56 #[doc = "Bit 2 - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."]
57 #[inline(always)]
58 pub fn dma_reset(&self) -> DMA_RESET_R {
59 DMA_RESET_R::new(((self.bits >> 2) & 1) != 0)
60 }
61 #[doc = "Bit 4 - Global interrupt enable/disable bit. 0: Disable; 1: Enable."]
62 #[inline(always)]
63 pub fn int_enable(&self) -> INT_ENABLE_R {
64 INT_ENABLE_R::new(((self.bits >> 4) & 1) != 0)
65 }
66 #[doc = "Bit 6 - For sending read-wait to SDIO cards."]
67 #[inline(always)]
68 pub fn read_wait(&self) -> READ_WAIT_R {
69 READ_WAIT_R::new(((self.bits >> 6) & 1) != 0)
70 }
71 #[doc = "Bit 7 - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."]
72 #[inline(always)]
73 pub fn send_irq_response(&self) -> SEND_IRQ_RESPONSE_R {
74 SEND_IRQ_RESPONSE_R::new(((self.bits >> 7) & 1) != 0)
75 }
76 #[doc = "Bit 8 - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."]
77 #[inline(always)]
78 pub fn abort_read_data(&self) -> ABORT_READ_DATA_R {
79 ABORT_READ_DATA_R::new(((self.bits >> 8) & 1) != 0)
80 }
81 #[doc = "Bit 9 - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."]
82 #[inline(always)]
83 pub fn send_ccsd(&self) -> SEND_CCSD_R {
84 SEND_CCSD_R::new(((self.bits >> 9) & 1) != 0)
85 }
86 #[doc = "Bit 10 - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."]
87 #[inline(always)]
88 pub fn send_auto_stop_ccsd(&self) -> SEND_AUTO_STOP_CCSD_R {
89 SEND_AUTO_STOP_CCSD_R::new(((self.bits >> 10) & 1) != 0)
90 }
91 #[doc = "Bit 11 - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."]
92 #[inline(always)]
93 pub fn ceata_device_interrupt_status(&self) -> CEATA_DEVICE_INTERRUPT_STATUS_R {
94 CEATA_DEVICE_INTERRUPT_STATUS_R::new(((self.bits >> 11) & 1) != 0)
95 }
96}
97#[cfg(feature = "impl-register-debug")]
98impl core::fmt::Debug for R {
99 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
100 f.debug_struct("CTRL")
101 .field("controller_reset", &self.controller_reset())
102 .field("fifo_reset", &self.fifo_reset())
103 .field("dma_reset", &self.dma_reset())
104 .field("int_enable", &self.int_enable())
105 .field("read_wait", &self.read_wait())
106 .field("send_irq_response", &self.send_irq_response())
107 .field("abort_read_data", &self.abort_read_data())
108 .field("send_ccsd", &self.send_ccsd())
109 .field("send_auto_stop_ccsd", &self.send_auto_stop_ccsd())
110 .field(
111 "ceata_device_interrupt_status",
112 &self.ceata_device_interrupt_status(),
113 )
114 .finish()
115 }
116}
117impl W {
118 #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
119 #[inline(always)]
120 pub fn controller_reset(&mut self) -> CONTROLLER_RESET_W<CTRL_SPEC> {
121 CONTROLLER_RESET_W::new(self, 0)
122 }
123 #[doc = "Bit 1 - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."]
124 #[inline(always)]
125 pub fn fifo_reset(&mut self) -> FIFO_RESET_W<CTRL_SPEC> {
126 FIFO_RESET_W::new(self, 1)
127 }
128 #[doc = "Bit 2 - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."]
129 #[inline(always)]
130 pub fn dma_reset(&mut self) -> DMA_RESET_W<CTRL_SPEC> {
131 DMA_RESET_W::new(self, 2)
132 }
133 #[doc = "Bit 4 - Global interrupt enable/disable bit. 0: Disable; 1: Enable."]
134 #[inline(always)]
135 pub fn int_enable(&mut self) -> INT_ENABLE_W<CTRL_SPEC> {
136 INT_ENABLE_W::new(self, 4)
137 }
138 #[doc = "Bit 6 - For sending read-wait to SDIO cards."]
139 #[inline(always)]
140 pub fn read_wait(&mut self) -> READ_WAIT_W<CTRL_SPEC> {
141 READ_WAIT_W::new(self, 6)
142 }
143 #[doc = "Bit 7 - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."]
144 #[inline(always)]
145 pub fn send_irq_response(&mut self) -> SEND_IRQ_RESPONSE_W<CTRL_SPEC> {
146 SEND_IRQ_RESPONSE_W::new(self, 7)
147 }
148 #[doc = "Bit 8 - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."]
149 #[inline(always)]
150 pub fn abort_read_data(&mut self) -> ABORT_READ_DATA_W<CTRL_SPEC> {
151 ABORT_READ_DATA_W::new(self, 8)
152 }
153 #[doc = "Bit 9 - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."]
154 #[inline(always)]
155 pub fn send_ccsd(&mut self) -> SEND_CCSD_W<CTRL_SPEC> {
156 SEND_CCSD_W::new(self, 9)
157 }
158 #[doc = "Bit 10 - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."]
159 #[inline(always)]
160 pub fn send_auto_stop_ccsd(&mut self) -> SEND_AUTO_STOP_CCSD_W<CTRL_SPEC> {
161 SEND_AUTO_STOP_CCSD_W::new(self, 10)
162 }
163 #[doc = "Bit 11 - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."]
164 #[inline(always)]
165 pub fn ceata_device_interrupt_status(&mut self) -> CEATA_DEVICE_INTERRUPT_STATUS_W<CTRL_SPEC> {
166 CEATA_DEVICE_INTERRUPT_STATUS_W::new(self, 11)
167 }
168}
169#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
170pub struct CTRL_SPEC;
171impl crate::RegisterSpec for CTRL_SPEC {
172 type Ux = u32;
173}
174#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
175impl crate::Readable for CTRL_SPEC {}
176#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
177impl crate::Writable for CTRL_SPEC {
178 type Safety = crate::Unsafe;
179 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
180 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
181}
182#[doc = "`reset()` method sets CTRL to value 0"]
183impl crate::Resettable for CTRL_SPEC {
184 const RESET_VALUE: u32 = 0;
185}