esp32s3/apb_ctrl/
sysclk_conf.rs

1#[doc = "Register `SYSCLK_CONF` reader"]
2pub type R = crate::R<SYSCLK_CONF_SPEC>;
3#[doc = "Register `SYSCLK_CONF` writer"]
4pub type W = crate::W<SYSCLK_CONF_SPEC>;
5#[doc = "Field `PRE_DIV_CNT` reader - ******* Description ***********"]
6pub type PRE_DIV_CNT_R = crate::FieldReader<u16>;
7#[doc = "Field `PRE_DIV_CNT` writer - ******* Description ***********"]
8pub type PRE_DIV_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
9#[doc = "Field `CLK_320M_EN` reader - ******* Description ***********"]
10pub type CLK_320M_EN_R = crate::BitReader;
11#[doc = "Field `CLK_320M_EN` writer - ******* Description ***********"]
12pub type CLK_320M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CLK_EN` reader - ******* Description ***********"]
14pub type CLK_EN_R = crate::BitReader;
15#[doc = "Field `CLK_EN` writer - ******* Description ***********"]
16pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RST_TICK_CNT` reader - ******* Description ***********"]
18pub type RST_TICK_CNT_R = crate::BitReader;
19#[doc = "Field `RST_TICK_CNT` writer - ******* Description ***********"]
20pub type RST_TICK_CNT_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:9 - ******* Description ***********"]
23    #[inline(always)]
24    pub fn pre_div_cnt(&self) -> PRE_DIV_CNT_R {
25        PRE_DIV_CNT_R::new((self.bits & 0x03ff) as u16)
26    }
27    #[doc = "Bit 10 - ******* Description ***********"]
28    #[inline(always)]
29    pub fn clk_320m_en(&self) -> CLK_320M_EN_R {
30        CLK_320M_EN_R::new(((self.bits >> 10) & 1) != 0)
31    }
32    #[doc = "Bit 11 - ******* Description ***********"]
33    #[inline(always)]
34    pub fn clk_en(&self) -> CLK_EN_R {
35        CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
36    }
37    #[doc = "Bit 12 - ******* Description ***********"]
38    #[inline(always)]
39    pub fn rst_tick_cnt(&self) -> RST_TICK_CNT_R {
40        RST_TICK_CNT_R::new(((self.bits >> 12) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("SYSCLK_CONF")
47            .field("pre_div_cnt", &self.pre_div_cnt())
48            .field("clk_320m_en", &self.clk_320m_en())
49            .field("clk_en", &self.clk_en())
50            .field("rst_tick_cnt", &self.rst_tick_cnt())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:9 - ******* Description ***********"]
56    #[inline(always)]
57    pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<SYSCLK_CONF_SPEC> {
58        PRE_DIV_CNT_W::new(self, 0)
59    }
60    #[doc = "Bit 10 - ******* Description ***********"]
61    #[inline(always)]
62    pub fn clk_320m_en(&mut self) -> CLK_320M_EN_W<SYSCLK_CONF_SPEC> {
63        CLK_320M_EN_W::new(self, 10)
64    }
65    #[doc = "Bit 11 - ******* Description ***********"]
66    #[inline(always)]
67    pub fn clk_en(&mut self) -> CLK_EN_W<SYSCLK_CONF_SPEC> {
68        CLK_EN_W::new(self, 11)
69    }
70    #[doc = "Bit 12 - ******* Description ***********"]
71    #[inline(always)]
72    pub fn rst_tick_cnt(&mut self) -> RST_TICK_CNT_W<SYSCLK_CONF_SPEC> {
73        RST_TICK_CNT_W::new(self, 12)
74    }
75}
76#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`sysclk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysclk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct SYSCLK_CONF_SPEC;
78impl crate::RegisterSpec for SYSCLK_CONF_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`sysclk_conf::R`](R) reader structure"]
82impl crate::Readable for SYSCLK_CONF_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`sysclk_conf::W`](W) writer structure"]
84impl crate::Writable for SYSCLK_CONF_SPEC {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets SYSCLK_CONF to value 0x01"]
90impl crate::Resettable for SYSCLK_CONF_SPEC {
91    const RESET_VALUE: u32 = 0x01;
92}
esp32s3/apb_ctrl/sysclk_conf.rs

esp32s3/apb_ctrl/
sysclk_conf.rs
