Struct esp32s3::pwm0::int_ena::W

pub struct W(_);

Register INT_ENA writer

Implementations

impl W

pub fn timer0_stop_int_ena(&mut self) -> TIMER0_STOP_INT_ENA_W<'_, 0>

Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops.

pub fn timer1_stop_int_ena(&mut self) -> TIMER1_STOP_INT_ENA_W<'_, 1>

Bit 1 - The enable bit for the interrupt triggered when the timer 1 stops.

pub fn timer2_stop_int_ena(&mut self) -> TIMER2_STOP_INT_ENA_W<'_, 2>

Bit 2 - The enable bit for the interrupt triggered when the timer 2 stops.

pub fn timer0_tez_int_ena(&mut self) -> TIMER0_TEZ_INT_ENA_W<'_, 3>

Bit 3 - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.

pub fn timer1_tez_int_ena(&mut self) -> TIMER1_TEZ_INT_ENA_W<'_, 4>

Bit 4 - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.

pub fn timer2_tez_int_ena(&mut self) -> TIMER2_TEZ_INT_ENA_W<'_, 5>

Bit 5 - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.

pub fn timer0_tep_int_ena(&mut self) -> TIMER0_TEP_INT_ENA_W<'_, 6>

Bit 6 - The enable bit for the interrupt triggered by a PWM timer 0 TEP event.

pub fn timer1_tep_int_ena(&mut self) -> TIMER1_TEP_INT_ENA_W<'_, 7>

Bit 7 - The enable bit for the interrupt triggered by a PWM timer 1 TEP event.

pub fn timer2_tep_int_ena(&mut self) -> TIMER2_TEP_INT_ENA_W<'_, 8>

Bit 8 - The enable bit for the interrupt triggered by a PWM timer 2 TEP event.

pub fn fault0_int_ena(&mut self) -> FAULT0_INT_ENA_W<'_, 9>

Bit 9 - The enable bit for the interrupt triggered when event_f0 starts.

pub fn fault1_int_ena(&mut self) -> FAULT1_INT_ENA_W<'_, 10>

Bit 10 - The enable bit for the interrupt triggered when event_f1 starts.

pub fn fault2_int_ena(&mut self) -> FAULT2_INT_ENA_W<'_, 11>

Bit 11 - The enable bit for the interrupt triggered when event_f2 starts.

pub fn fault0_clr_int_ena(&mut self) -> FAULT0_CLR_INT_ENA_W<'_, 12>

Bit 12 - The enable bit for the interrupt triggered when event_f0 ends.

pub fn fault1_clr_int_ena(&mut self) -> FAULT1_CLR_INT_ENA_W<'_, 13>

Bit 13 - The enable bit for the interrupt triggered when event_f1 ends.

pub fn fault2_clr_int_ena(&mut self) -> FAULT2_CLR_INT_ENA_W<'_, 14>

Bit 14 - The enable bit for the interrupt triggered when event_f2 ends.

pub fn cmpr0_tea_int_ena(&mut self) -> CMPR0_TEA_INT_ENA_W<'_, 15>

Bit 15 - The enable bit for the interrupt triggered by a PWM operator 0 TEA event

pub fn cmpr1_tea_int_ena(&mut self) -> CMPR1_TEA_INT_ENA_W<'_, 16>

Bit 16 - The enable bit for the interrupt triggered by a PWM operator 1 TEA event

pub fn cmpr2_tea_int_ena(&mut self) -> CMPR2_TEA_INT_ENA_W<'_, 17>

Bit 17 - The enable bit for the interrupt triggered by a PWM operator 2 TEA event

pub fn cmpr0_teb_int_ena(&mut self) -> CMPR0_TEB_INT_ENA_W<'_, 18>

Bit 18 - The enable bit for the interrupt triggered by a PWM operator 0 TEB event

pub fn cmpr1_teb_int_ena(&mut self) -> CMPR1_TEB_INT_ENA_W<'_, 19>

Bit 19 - The enable bit for the interrupt triggered by a PWM operator 1 TEB event

pub fn cmpr2_teb_int_ena(&mut self) -> CMPR2_TEB_INT_ENA_W<'_, 20>

Bit 20 - The enable bit for the interrupt triggered by a PWM operator 2 TEB event

pub fn tz0_cbc_int_ena(&mut self) -> TZ0_CBC_INT_ENA_W<'_, 21>

Bit 21 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.

pub fn tz1_cbc_int_ena(&mut self) -> TZ1_CBC_INT_ENA_W<'_, 22>

Bit 22 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.

pub fn tz2_cbc_int_ena(&mut self) -> TZ2_CBC_INT_ENA_W<'_, 23>

Bit 23 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.

pub fn tz0_ost_int_ena(&mut self) -> TZ0_OST_INT_ENA_W<'_, 24>

Bit 24 - The enable bit for the interrupt triggered by a one-shot mode action on PWM0.

pub fn tz1_ost_int_ena(&mut self) -> TZ1_OST_INT_ENA_W<'_, 25>

Bit 25 - The enable bit for the interrupt triggered by a one-shot mode action on PWM1.

pub fn tz2_ost_int_ena(&mut self) -> TZ2_OST_INT_ENA_W<'_, 26>

Bit 26 - The enable bit for the interrupt triggered by a one-shot mode action on PWM2.

pub fn cap0_int_ena(&mut self) -> CAP0_INT_ENA_W<'_, 27>

Bit 27 - The enable bit for the interrupt triggered by capture on channel 0.

pub fn cap1_int_ena(&mut self) -> CAP1_INT_ENA_W<'_, 28>

Bit 28 - The enable bit for the interrupt triggered by capture on channel 1.

pub fn cap2_int_ena(&mut self) -> CAP2_INT_ENA_W<'_, 29>

Bit 29 - The enable bit for the interrupt triggered by capture on channel 2.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<INT_ENA_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<INT_ENA_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<INT_ENA_SPEC>> for W

fn from(writer: W<INT_ENA_SPEC>) -> Self

Converts to this type from the input type.