Struct esp32s3_hal::gpio::Pins

source · 
pub struct Pins {
Show 45 fields
    pub gpio0: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio0Signals, 0>,
    pub gpio1: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio1Signals, 1>,
    pub gpio2: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio2Signals, 2>,
    pub gpio3: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio3Signals, 3>,
    pub gpio4: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio4Signals, 4>,
    pub gpio5: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio5Signals, 5>,
    pub gpio6: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio6Signals, 6>,
    pub gpio7: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio7Signals, 7>,
    pub gpio8: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio8Signals, 8>,
    pub gpio9: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio9Signals, 9>,
    pub gpio10: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio10Signals, 10>,
    pub gpio11: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio11Signals, 11>,
    pub gpio12: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio12Signals, 12>,
    pub gpio13: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio13Signals, 13>,
    pub gpio14: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio14Signals, 14>,
    pub gpio15: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio15Signals, 15>,
    pub gpio16: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio16Signals, 16>,
    pub gpio17: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio17Signals, 17>,
    pub gpio18: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio18Signals, 18>,
    pub gpio19: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio19Signals, 19>,
    pub gpio20: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio20Signals, 20>,
    pub gpio21: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio21Signals, 21>,
    pub gpio26: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio26Signals, 26>,
    pub gpio27: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio27Signals, 27>,
    pub gpio28: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio28Signals, 28>,
    pub gpio29: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio29Signals, 29>,
    pub gpio30: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio30Signals, 30>,
    pub gpio31: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio31Signals, 31>,
    pub gpio32: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio32Signals, 32>,
    pub gpio33: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio33Signals, 33>,
    pub gpio34: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio34Signals, 34>,
    pub gpio35: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio35Signals, 35>,
    pub gpio36: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio36Signals, 36>,
    pub gpio37: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio37Signals, 37>,
    pub gpio38: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio38Signals, 38>,
    pub gpio39: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio39Signals, 39>,
    pub gpio40: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio40Signals, 40>,
    pub gpio41: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio41Signals, 41>,
    pub gpio42: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio42Signals, 42>,
    pub gpio43: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio43Signals, 43>,
    pub gpio44: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio44Signals, 44>,
    pub gpio45: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio45Signals, 45>,
    pub gpio46: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio46Signals, 46>,
    pub gpio47: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio47Signals, 47>,
    pub gpio48: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio48Signals, 48>,

}

Fields§

§gpio0: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio0Signals, 0>§gpio1: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio1Signals, 1>§gpio2: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio2Signals, 2>§gpio3: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio3Signals, 3>§gpio4: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio4Signals, 4>§gpio5: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio5Signals, 5>§gpio6: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio6Signals, 6>§gpio7: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio7Signals, 7>§gpio8: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio8Signals, 8>§gpio9: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio9Signals, 9>§gpio10: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio10Signals, 10>§gpio11: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio11Signals, 11>§gpio12: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio12Signals, 12>§gpio13: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio13Signals, 13>§gpio14: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio14Signals, 14>§gpio15: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio15Signals, 15>§gpio16: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio16Signals, 16>§gpio17: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio17Signals, 17>§gpio18: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio18Signals, 18>§gpio19: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio19Signals, 19>§gpio20: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio20Signals, 20>§gpio21: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputAnalogPinType, Gpio21Signals, 21>§gpio26: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio26Signals, 26>§gpio27: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio27Signals, 27>§gpio28: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio28Signals, 28>§gpio29: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio29Signals, 29>§gpio30: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio30Signals, 30>§gpio31: GpioPin<Unknown, Bank0GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank0, InputOutputPinType, Gpio31Signals, 31>§gpio32: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio32Signals, 32>§gpio33: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio33Signals, 33>§gpio34: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio34Signals, 34>§gpio35: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio35Signals, 35>§gpio36: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio36Signals, 36>§gpio37: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio37Signals, 37>§gpio38: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio38Signals, 38>§gpio39: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio39Signals, 39>§gpio40: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio40Signals, 40>§gpio41: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio41Signals, 41>§gpio42: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio42Signals, 42>§gpio43: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio43Signals, 43>§gpio44: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio44Signals, 44>§gpio45: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio45Signals, 45>§gpio46: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio46Signals, 46>§gpio47: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio47Signals, 47>§gpio48: GpioPin<Unknown, Bank1GpioRegisterAccess, SingleCoreInteruptStatusRegisterAccessBank1, InputOutputPinType, Gpio48Signals, 48>

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