1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 rom_ctrl_0: ROM_CTRL_0,
6 rom_ctrl_1: ROM_CTRL_1,
7 sram_ctrl_0: SRAM_CTRL_0,
8 sram_ctrl_1: SRAM_CTRL_1,
9 cpu_peri_clk_en: CPU_PERI_CLK_EN,
10 cpu_peri_rst_en: CPU_PERI_RST_EN,
11 cpu_per_conf: CPU_PER_CONF,
12 jtag_ctrl_0: JTAG_CTRL_0,
13 jtag_ctrl_1: JTAG_CTRL_1,
14 jtag_ctrl_2: JTAG_CTRL_2,
15 jtag_ctrl_3: JTAG_CTRL_3,
16 jtag_ctrl_4: JTAG_CTRL_4,
17 jtag_ctrl_5: JTAG_CTRL_5,
18 jtag_ctrl_6: JTAG_CTRL_6,
19 jtag_ctrl_7: JTAG_CTRL_7,
20 mem_pd_mask: MEM_PD_MASK,
21 perip_clk_en0: PERIP_CLK_EN0,
22 perip_clk_en1: PERIP_CLK_EN1,
23 perip_rst_en0: PERIP_RST_EN0,
24 perip_rst_en1: PERIP_RST_EN1,
25 lpck_div_int: LPCK_DIV_INT,
26 bt_lpck_div_frac: BT_LPCK_DIV_FRAC,
27 cpu_intr_from_cpu_0: CPU_INTR_FROM_CPU_0,
28 cpu_intr_from_cpu_1: CPU_INTR_FROM_CPU_1,
29 cpu_intr_from_cpu_2: CPU_INTR_FROM_CPU_2,
30 cpu_intr_from_cpu_3: CPU_INTR_FROM_CPU_3,
31 rsa_pd_ctrl: RSA_PD_CTRL,
32 bustoextmem_ena: BUSTOEXTMEM_ENA,
33 cache_control: CACHE_CONTROL,
34 external_device_encrypt_decrypt_control: EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL,
35 rtc_fastmem_config: RTC_FASTMEM_CONFIG,
36 rtc_fastmem_crc: RTC_FASTMEM_CRC,
37 redundant_eco_ctrl: REDUNDANT_ECO_CTRL,
38 clock_gate: CLOCK_GATE,
39 sram_ctrl_2: SRAM_CTRL_2,
40 sysclk_conf: SYSCLK_CONF,
41 _reserved36: [u8; 0x0f6c],
42 date: DATE,
43}
44impl RegisterBlock {
45 #[doc = "0x00 - System ROM configuration register 0"]
46 #[inline(always)]
47 pub const fn rom_ctrl_0(&self) -> &ROM_CTRL_0 {
48 &self.rom_ctrl_0
49 }
50 #[doc = "0x04 - System ROM configuration register 1"]
51 #[inline(always)]
52 pub const fn rom_ctrl_1(&self) -> &ROM_CTRL_1 {
53 &self.rom_ctrl_1
54 }
55 #[doc = "0x08 - System SRAM configuration register 0"]
56 #[inline(always)]
57 pub const fn sram_ctrl_0(&self) -> &SRAM_CTRL_0 {
58 &self.sram_ctrl_0
59 }
60 #[doc = "0x0c - System SRAM configuration register 1"]
61 #[inline(always)]
62 pub const fn sram_ctrl_1(&self) -> &SRAM_CTRL_1 {
63 &self.sram_ctrl_1
64 }
65 #[doc = "0x10 - CPU peripheral clock enable register"]
66 #[inline(always)]
67 pub const fn cpu_peri_clk_en(&self) -> &CPU_PERI_CLK_EN {
68 &self.cpu_peri_clk_en
69 }
70 #[doc = "0x14 - CPU peripheral reset register"]
71 #[inline(always)]
72 pub const fn cpu_peri_rst_en(&self) -> &CPU_PERI_RST_EN {
73 &self.cpu_peri_rst_en
74 }
75 #[doc = "0x18 - CPU peripheral clock configuration register"]
76 #[inline(always)]
77 pub const fn cpu_per_conf(&self) -> &CPU_PER_CONF {
78 &self.cpu_per_conf
79 }
80 #[doc = "0x1c - JTAG configuration register 0"]
81 #[inline(always)]
82 pub const fn jtag_ctrl_0(&self) -> &JTAG_CTRL_0 {
83 &self.jtag_ctrl_0
84 }
85 #[doc = "0x20 - JTAG configuration register 1"]
86 #[inline(always)]
87 pub const fn jtag_ctrl_1(&self) -> &JTAG_CTRL_1 {
88 &self.jtag_ctrl_1
89 }
90 #[doc = "0x24 - JTAG configuration register 2"]
91 #[inline(always)]
92 pub const fn jtag_ctrl_2(&self) -> &JTAG_CTRL_2 {
93 &self.jtag_ctrl_2
94 }
95 #[doc = "0x28 - JTAG configuration register 3"]
96 #[inline(always)]
97 pub const fn jtag_ctrl_3(&self) -> &JTAG_CTRL_3 {
98 &self.jtag_ctrl_3
99 }
100 #[doc = "0x2c - JTAG configuration register 4"]
101 #[inline(always)]
102 pub const fn jtag_ctrl_4(&self) -> &JTAG_CTRL_4 {
103 &self.jtag_ctrl_4
104 }
105 #[doc = "0x30 - JTAG configuration register 5"]
106 #[inline(always)]
107 pub const fn jtag_ctrl_5(&self) -> &JTAG_CTRL_5 {
108 &self.jtag_ctrl_5
109 }
110 #[doc = "0x34 - JTAG configuration register 6"]
111 #[inline(always)]
112 pub const fn jtag_ctrl_6(&self) -> &JTAG_CTRL_6 {
113 &self.jtag_ctrl_6
114 }
115 #[doc = "0x38 - JTAG configuration register 7"]
116 #[inline(always)]
117 pub const fn jtag_ctrl_7(&self) -> &JTAG_CTRL_7 {
118 &self.jtag_ctrl_7
119 }
120 #[doc = "0x3c - Memory power-related controlling register (under low-sleep)"]
121 #[inline(always)]
122 pub const fn mem_pd_mask(&self) -> &MEM_PD_MASK {
123 &self.mem_pd_mask
124 }
125 #[doc = "0x40 - System peripheral clock (for hardware accelerators) enable register"]
126 #[inline(always)]
127 pub const fn perip_clk_en0(&self) -> &PERIP_CLK_EN0 {
128 &self.perip_clk_en0
129 }
130 #[doc = "0x44 - System peripheral clock (for hardware accelerators) enable register 1"]
131 #[inline(always)]
132 pub const fn perip_clk_en1(&self) -> &PERIP_CLK_EN1 {
133 &self.perip_clk_en1
134 }
135 #[doc = "0x48 - System peripheral (hardware accelerators) reset register 0"]
136 #[inline(always)]
137 pub const fn perip_rst_en0(&self) -> &PERIP_RST_EN0 {
138 &self.perip_rst_en0
139 }
140 #[doc = "0x4c - System peripheral (hardware accelerators) reset register 1"]
141 #[inline(always)]
142 pub const fn perip_rst_en1(&self) -> &PERIP_RST_EN1 {
143 &self.perip_rst_en1
144 }
145 #[doc = "0x50 - Low power clock divider integer register"]
146 #[inline(always)]
147 pub const fn lpck_div_int(&self) -> &LPCK_DIV_INT {
148 &self.lpck_div_int
149 }
150 #[doc = "0x54 - Divider fraction configuration register for low-power clock"]
151 #[inline(always)]
152 pub const fn bt_lpck_div_frac(&self) -> &BT_LPCK_DIV_FRAC {
153 &self.bt_lpck_div_frac
154 }
155 #[doc = "0x58 - CPU interrupt controlling register 0"]
156 #[inline(always)]
157 pub const fn cpu_intr_from_cpu_0(&self) -> &CPU_INTR_FROM_CPU_0 {
158 &self.cpu_intr_from_cpu_0
159 }
160 #[doc = "0x5c - CPU interrupt controlling register 1"]
161 #[inline(always)]
162 pub const fn cpu_intr_from_cpu_1(&self) -> &CPU_INTR_FROM_CPU_1 {
163 &self.cpu_intr_from_cpu_1
164 }
165 #[doc = "0x60 - CPU interrupt controlling register 2"]
166 #[inline(always)]
167 pub const fn cpu_intr_from_cpu_2(&self) -> &CPU_INTR_FROM_CPU_2 {
168 &self.cpu_intr_from_cpu_2
169 }
170 #[doc = "0x64 - CPU interrupt controlling register 3"]
171 #[inline(always)]
172 pub const fn cpu_intr_from_cpu_3(&self) -> &CPU_INTR_FROM_CPU_3 {
173 &self.cpu_intr_from_cpu_3
174 }
175 #[doc = "0x68 - RSA memory remapping register"]
176 #[inline(always)]
177 pub const fn rsa_pd_ctrl(&self) -> &RSA_PD_CTRL {
178 &self.rsa_pd_ctrl
179 }
180 #[doc = "0x6c - EDMA enable register"]
181 #[inline(always)]
182 pub const fn bustoextmem_ena(&self) -> &BUSTOEXTMEM_ENA {
183 &self.bustoextmem_ena
184 }
185 #[doc = "0x70 - Cache control register"]
186 #[inline(always)]
187 pub const fn cache_control(&self) -> &CACHE_CONTROL {
188 &self.cache_control
189 }
190 #[doc = "0x74 - External memory encrypt and decrypt controlling register"]
191 #[inline(always)]
192 pub const fn external_device_encrypt_decrypt_control(
193 &self,
194 ) -> &EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL {
195 &self.external_device_encrypt_decrypt_control
196 }
197 #[doc = "0x78 - RTC fast memory configuration register"]
198 #[inline(always)]
199 pub const fn rtc_fastmem_config(&self) -> &RTC_FASTMEM_CONFIG {
200 &self.rtc_fastmem_config
201 }
202 #[doc = "0x7c - RTC fast memory CRC controlling register"]
203 #[inline(always)]
204 pub const fn rtc_fastmem_crc(&self) -> &RTC_FASTMEM_CRC {
205 &self.rtc_fastmem_crc
206 }
207 #[doc = "0x80 - Redundant ECO control register"]
208 #[inline(always)]
209 pub const fn redundant_eco_ctrl(&self) -> &REDUNDANT_ECO_CTRL {
210 &self.redundant_eco_ctrl
211 }
212 #[doc = "0x84 - Clock gate control register"]
213 #[inline(always)]
214 pub const fn clock_gate(&self) -> &CLOCK_GATE {
215 &self.clock_gate
216 }
217 #[doc = "0x88 - System SRAM configuration register 2"]
218 #[inline(always)]
219 pub const fn sram_ctrl_2(&self) -> &SRAM_CTRL_2 {
220 &self.sram_ctrl_2
221 }
222 #[doc = "0x8c - SoC clock configuration register"]
223 #[inline(always)]
224 pub const fn sysclk_conf(&self) -> &SYSCLK_CONF {
225 &self.sysclk_conf
226 }
227 #[doc = "0xffc - Version control register"]
228 #[inline(always)]
229 pub const fn date(&self) -> &DATE {
230 &self.date
231 }
232}
233#[doc = "ROM_CTRL_0 (rw) register accessor: System ROM configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_ctrl_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_ctrl_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_ctrl_0`] module"]
234pub type ROM_CTRL_0 = crate::Reg<rom_ctrl_0::ROM_CTRL_0_SPEC>;
235#[doc = "System ROM configuration register 0"]
236pub mod rom_ctrl_0;
237#[doc = "ROM_CTRL_1 (rw) register accessor: System ROM configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_ctrl_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_ctrl_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_ctrl_1`] module"]
238pub type ROM_CTRL_1 = crate::Reg<rom_ctrl_1::ROM_CTRL_1_SPEC>;
239#[doc = "System ROM configuration register 1"]
240pub mod rom_ctrl_1;
241#[doc = "SRAM_CTRL_0 (rw) register accessor: System SRAM configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ctrl_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ctrl_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ctrl_0`] module"]
242pub type SRAM_CTRL_0 = crate::Reg<sram_ctrl_0::SRAM_CTRL_0_SPEC>;
243#[doc = "System SRAM configuration register 0"]
244pub mod sram_ctrl_0;
245#[doc = "SRAM_CTRL_1 (rw) register accessor: System SRAM configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ctrl_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ctrl_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ctrl_1`] module"]
246pub type SRAM_CTRL_1 = crate::Reg<sram_ctrl_1::SRAM_CTRL_1_SPEC>;
247#[doc = "System SRAM configuration register 1"]
248pub mod sram_ctrl_1;
249#[doc = "CPU_PERI_CLK_EN (rw) register accessor: CPU peripheral clock enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_peri_clk_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_peri_clk_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_peri_clk_en`] module"]
250pub type CPU_PERI_CLK_EN = crate::Reg<cpu_peri_clk_en::CPU_PERI_CLK_EN_SPEC>;
251#[doc = "CPU peripheral clock enable register"]
252pub mod cpu_peri_clk_en;
253#[doc = "CPU_PERI_RST_EN (rw) register accessor: CPU peripheral reset register\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_peri_rst_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_peri_rst_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_peri_rst_en`] module"]
254pub type CPU_PERI_RST_EN = crate::Reg<cpu_peri_rst_en::CPU_PERI_RST_EN_SPEC>;
255#[doc = "CPU peripheral reset register"]
256pub mod cpu_peri_rst_en;
257#[doc = "CPU_PER_CONF (rw) register accessor: CPU peripheral clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_per_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_per_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_per_conf`] module"]
258pub type CPU_PER_CONF = crate::Reg<cpu_per_conf::CPU_PER_CONF_SPEC>;
259#[doc = "CPU peripheral clock configuration register"]
260pub mod cpu_per_conf;
261#[doc = "JTAG_CTRL_0 (w) register accessor: JTAG configuration register 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jtag_ctrl_0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_ctrl_0`] module"]
262pub type JTAG_CTRL_0 = crate::Reg<jtag_ctrl_0::JTAG_CTRL_0_SPEC>;
263#[doc = "JTAG configuration register 0"]
264pub mod jtag_ctrl_0;
265#[doc = "JTAG_CTRL_1 (w) register accessor: JTAG configuration register 1\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jtag_ctrl_1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_ctrl_1`] module"]
266pub type JTAG_CTRL_1 = crate::Reg<jtag_ctrl_1::JTAG_CTRL_1_SPEC>;
267#[doc = "JTAG configuration register 1"]
268pub mod jtag_ctrl_1;
269#[doc = "JTAG_CTRL_2 (w) register accessor: JTAG configuration register 2\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jtag_ctrl_2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_ctrl_2`] module"]
270pub type JTAG_CTRL_2 = crate::Reg<jtag_ctrl_2::JTAG_CTRL_2_SPEC>;
271#[doc = "JTAG configuration register 2"]
272pub mod jtag_ctrl_2;
273#[doc = "JTAG_CTRL_3 (w) register accessor: JTAG configuration register 3\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jtag_ctrl_3::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_ctrl_3`] module"]
274pub type JTAG_CTRL_3 = crate::Reg<jtag_ctrl_3::JTAG_CTRL_3_SPEC>;
275#[doc = "JTAG configuration register 3"]
276pub mod jtag_ctrl_3;
277#[doc = "JTAG_CTRL_4 (w) register accessor: JTAG configuration register 4\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jtag_ctrl_4::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_ctrl_4`] module"]
278pub type JTAG_CTRL_4 = crate::Reg<jtag_ctrl_4::JTAG_CTRL_4_SPEC>;
279#[doc = "JTAG configuration register 4"]
280pub mod jtag_ctrl_4;
281#[doc = "JTAG_CTRL_5 (w) register accessor: JTAG configuration register 5\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jtag_ctrl_5::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_ctrl_5`] module"]
282pub type JTAG_CTRL_5 = crate::Reg<jtag_ctrl_5::JTAG_CTRL_5_SPEC>;
283#[doc = "JTAG configuration register 5"]
284pub mod jtag_ctrl_5;
285#[doc = "JTAG_CTRL_6 (w) register accessor: JTAG configuration register 6\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jtag_ctrl_6::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_ctrl_6`] module"]
286pub type JTAG_CTRL_6 = crate::Reg<jtag_ctrl_6::JTAG_CTRL_6_SPEC>;
287#[doc = "JTAG configuration register 6"]
288pub mod jtag_ctrl_6;
289#[doc = "JTAG_CTRL_7 (w) register accessor: JTAG configuration register 7\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jtag_ctrl_7::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@jtag_ctrl_7`] module"]
290pub type JTAG_CTRL_7 = crate::Reg<jtag_ctrl_7::JTAG_CTRL_7_SPEC>;
291#[doc = "JTAG configuration register 7"]
292pub mod jtag_ctrl_7;
293#[doc = "MEM_PD_MASK (rw) register accessor: Memory power-related controlling register (under low-sleep)\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_pd_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mem_pd_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_pd_mask`] module"]
294pub type MEM_PD_MASK = crate::Reg<mem_pd_mask::MEM_PD_MASK_SPEC>;
295#[doc = "Memory power-related controlling register (under low-sleep)"]
296pub mod mem_pd_mask;
297#[doc = "PERIP_CLK_EN0 (rw) register accessor: System peripheral clock (for hardware accelerators) enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_clk_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_clk_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perip_clk_en0`] module"]
298pub type PERIP_CLK_EN0 = crate::Reg<perip_clk_en0::PERIP_CLK_EN0_SPEC>;
299#[doc = "System peripheral clock (for hardware accelerators) enable register"]
300pub mod perip_clk_en0;
301#[doc = "PERIP_CLK_EN1 (rw) register accessor: System peripheral clock (for hardware accelerators) enable register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_clk_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_clk_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perip_clk_en1`] module"]
302pub type PERIP_CLK_EN1 = crate::Reg<perip_clk_en1::PERIP_CLK_EN1_SPEC>;
303#[doc = "System peripheral clock (for hardware accelerators) enable register 1"]
304pub mod perip_clk_en1;
305#[doc = "PERIP_RST_EN0 (rw) register accessor: System peripheral (hardware accelerators) reset register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_rst_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_rst_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perip_rst_en0`] module"]
306pub type PERIP_RST_EN0 = crate::Reg<perip_rst_en0::PERIP_RST_EN0_SPEC>;
307#[doc = "System peripheral (hardware accelerators) reset register 0"]
308pub mod perip_rst_en0;
309#[doc = "PERIP_RST_EN1 (rw) register accessor: System peripheral (hardware accelerators) reset register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`perip_rst_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perip_rst_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perip_rst_en1`] module"]
310pub type PERIP_RST_EN1 = crate::Reg<perip_rst_en1::PERIP_RST_EN1_SPEC>;
311#[doc = "System peripheral (hardware accelerators) reset register 1"]
312pub mod perip_rst_en1;
313#[doc = "LPCK_DIV_INT (rw) register accessor: Low power clock divider integer register\n\nYou can [`read`](crate::Reg::read) this register and get [`lpck_div_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpck_div_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpck_div_int`] module"]
314pub type LPCK_DIV_INT = crate::Reg<lpck_div_int::LPCK_DIV_INT_SPEC>;
315#[doc = "Low power clock divider integer register"]
316pub mod lpck_div_int;
317#[doc = "BT_LPCK_DIV_FRAC (rw) register accessor: Divider fraction configuration register for low-power clock\n\nYou can [`read`](crate::Reg::read) this register and get [`bt_lpck_div_frac::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bt_lpck_div_frac::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bt_lpck_div_frac`] module"]
318pub type BT_LPCK_DIV_FRAC = crate::Reg<bt_lpck_div_frac::BT_LPCK_DIV_FRAC_SPEC>;
319#[doc = "Divider fraction configuration register for low-power clock"]
320pub mod bt_lpck_div_frac;
321#[doc = "CPU_INTR_FROM_CPU_0 (rw) register accessor: CPU interrupt controlling register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_intr_from_cpu_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_intr_from_cpu_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_intr_from_cpu_0`] module"]
322pub type CPU_INTR_FROM_CPU_0 = crate::Reg<cpu_intr_from_cpu_0::CPU_INTR_FROM_CPU_0_SPEC>;
323#[doc = "CPU interrupt controlling register 0"]
324pub mod cpu_intr_from_cpu_0;
325#[doc = "CPU_INTR_FROM_CPU_1 (rw) register accessor: CPU interrupt controlling register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_intr_from_cpu_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_intr_from_cpu_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_intr_from_cpu_1`] module"]
326pub type CPU_INTR_FROM_CPU_1 = crate::Reg<cpu_intr_from_cpu_1::CPU_INTR_FROM_CPU_1_SPEC>;
327#[doc = "CPU interrupt controlling register 1"]
328pub mod cpu_intr_from_cpu_1;
329#[doc = "CPU_INTR_FROM_CPU_2 (rw) register accessor: CPU interrupt controlling register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_intr_from_cpu_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_intr_from_cpu_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_intr_from_cpu_2`] module"]
330pub type CPU_INTR_FROM_CPU_2 = crate::Reg<cpu_intr_from_cpu_2::CPU_INTR_FROM_CPU_2_SPEC>;
331#[doc = "CPU interrupt controlling register 2"]
332pub mod cpu_intr_from_cpu_2;
333#[doc = "CPU_INTR_FROM_CPU_3 (rw) register accessor: CPU interrupt controlling register 3\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_intr_from_cpu_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_intr_from_cpu_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_intr_from_cpu_3`] module"]
334pub type CPU_INTR_FROM_CPU_3 = crate::Reg<cpu_intr_from_cpu_3::CPU_INTR_FROM_CPU_3_SPEC>;
335#[doc = "CPU interrupt controlling register 3"]
336pub mod cpu_intr_from_cpu_3;
337#[doc = "RSA_PD_CTRL (rw) register accessor: RSA memory remapping register\n\nYou can [`read`](crate::Reg::read) this register and get [`rsa_pd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rsa_pd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rsa_pd_ctrl`] module"]
338pub type RSA_PD_CTRL = crate::Reg<rsa_pd_ctrl::RSA_PD_CTRL_SPEC>;
339#[doc = "RSA memory remapping register"]
340pub mod rsa_pd_ctrl;
341#[doc = "BUSTOEXTMEM_ENA (rw) register accessor: EDMA enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`bustoextmem_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bustoextmem_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bustoextmem_ena`] module"]
342pub type BUSTOEXTMEM_ENA = crate::Reg<bustoextmem_ena::BUSTOEXTMEM_ENA_SPEC>;
343#[doc = "EDMA enable register"]
344pub mod bustoextmem_ena;
345#[doc = "CACHE_CONTROL (rw) register accessor: Cache control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cache_control`] module"]
346pub type CACHE_CONTROL = crate::Reg<cache_control::CACHE_CONTROL_SPEC>;
347#[doc = "Cache control register"]
348pub mod cache_control;
349#[doc = "EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL (rw) register accessor: External memory encrypt and decrypt controlling register\n\nYou can [`read`](crate::Reg::read) this register and get [`external_device_encrypt_decrypt_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`external_device_encrypt_decrypt_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@external_device_encrypt_decrypt_control`] module"]
350pub type EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL = crate::Reg<
351 external_device_encrypt_decrypt_control::EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC,
352>;
353#[doc = "External memory encrypt and decrypt controlling register"]
354pub mod external_device_encrypt_decrypt_control;
355#[doc = "RTC_FASTMEM_CONFIG (rw) register accessor: RTC fast memory configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_fastmem_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_fastmem_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_fastmem_config`] module"]
356pub type RTC_FASTMEM_CONFIG = crate::Reg<rtc_fastmem_config::RTC_FASTMEM_CONFIG_SPEC>;
357#[doc = "RTC fast memory configuration register"]
358pub mod rtc_fastmem_config;
359#[doc = "RTC_FASTMEM_CRC (r) register accessor: RTC fast memory CRC controlling register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_fastmem_crc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_fastmem_crc`] module"]
360pub type RTC_FASTMEM_CRC = crate::Reg<rtc_fastmem_crc::RTC_FASTMEM_CRC_SPEC>;
361#[doc = "RTC fast memory CRC controlling register"]
362pub mod rtc_fastmem_crc;
363#[doc = "Redundant_ECO_Ctrl (rw) register accessor: Redundant ECO control register\n\nYou can [`read`](crate::Reg::read) this register and get [`redundant_eco_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`redundant_eco_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@redundant_eco_ctrl`] module"]
364#[doc(alias = "Redundant_ECO_Ctrl")]
365pub type REDUNDANT_ECO_CTRL = crate::Reg<redundant_eco_ctrl::REDUNDANT_ECO_CTRL_SPEC>;
366#[doc = "Redundant ECO control register"]
367pub mod redundant_eco_ctrl;
368#[doc = "CLOCK_GATE (rw) register accessor: Clock gate control register\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"]
369pub type CLOCK_GATE = crate::Reg<clock_gate::CLOCK_GATE_SPEC>;
370#[doc = "Clock gate control register"]
371pub mod clock_gate;
372#[doc = "SRAM_CTRL_2 (rw) register accessor: System SRAM configuration register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_ctrl_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_ctrl_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sram_ctrl_2`] module"]
373pub type SRAM_CTRL_2 = crate::Reg<sram_ctrl_2::SRAM_CTRL_2_SPEC>;
374#[doc = "System SRAM configuration register 2"]
375pub mod sram_ctrl_2;
376#[doc = "SYSCLK_CONF (rw) register accessor: SoC clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`sysclk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysclk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysclk_conf`] module"]
377pub type SYSCLK_CONF = crate::Reg<sysclk_conf::SYSCLK_CONF_SPEC>;
378#[doc = "SoC clock configuration register"]
379pub mod sysclk_conf;
380#[doc = "DATE (rw) register accessor: Version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
381pub type DATE = crate::Reg<date::DATE_SPEC>;
382#[doc = "Version control register"]
383pub mod date;