esp32s2/spi0/
cmd.rs

1#[doc = "Register `CMD` reader"]
2pub type R = crate::R<CMD_SPEC>;
3#[doc = "Register `CMD` writer"]
4pub type W = crate::W<CMD_SPEC>;
5#[doc = "Field `CONF_BITLEN` reader - Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state."]
6pub type CONF_BITLEN_R = crate::FieldReader<u32>;
7#[doc = "Field `CONF_BITLEN` writer - Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state."]
8pub type CONF_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>;
9#[doc = "Field `USR` reader - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
10pub type USR_R = crate::BitReader;
11#[doc = "Field `USR` writer - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
12pub type USR_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bits 0:22 - Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state."]
15    #[inline(always)]
16    pub fn conf_bitlen(&self) -> CONF_BITLEN_R {
17        CONF_BITLEN_R::new(self.bits & 0x007f_ffff)
18    }
19    #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
20    #[inline(always)]
21    pub fn usr(&self) -> USR_R {
22        USR_R::new(((self.bits >> 24) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CMD")
29            .field("conf_bitlen", &self.conf_bitlen())
30            .field("usr", &self.usr())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:22 - Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state."]
36    #[inline(always)]
37    pub fn conf_bitlen(&mut self) -> CONF_BITLEN_W<CMD_SPEC> {
38        CONF_BITLEN_W::new(self, 0)
39    }
40    #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
41    #[inline(always)]
42    pub fn usr(&mut self) -> USR_W<CMD_SPEC> {
43        USR_W::new(self, 24)
44    }
45}
46#[doc = "Command control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct CMD_SPEC;
48impl crate::RegisterSpec for CMD_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
52impl crate::Readable for CMD_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
54impl crate::Writable for CMD_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets CMD to value 0"]
60impl crate::Resettable for CMD_SPEC {
61    const RESET_VALUE: u32 = 0;
62}
esp32s2/spi0/cmd.rs

esp32s2/spi0/
cmd.rs
