1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `CH_TX_END(0-3)` writer - Set this bit to clear the CH%s_TX_END_INT interrupt."]
4pub type CH_TX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `CH_RX_END(0-3)` writer - Set this bit to clear the CH%s_RX_END_INT interrupt."]
6pub type CH_RX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `CH_ERR(0-3)` writer - Set this bit to clear the CH%s_ERR_INT interrupt."]
8pub type CH_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CH_TX_THR_EVENT(0-3)` writer - Set this bit to clear the CH%s_TX_THR_EVENT_INT interrupt."]
10pub type CH_TX_THR_EVENT_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `CH_TX_LOOP(0-3)` writer - Set this bit to clear the CH%s_TX_LOOP_INT interrupt."]
12pub type CH_TX_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[cfg(feature = "impl-register-debug")]
14impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
15 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
16 write!(f, "(not readable)")
17 }
18}
19impl W {
20 #[doc = "Set this bit to clear the CH(0-3)_TX_END_INT interrupt."]
21 #[doc = ""]
22 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
23 #[inline(always)]
24 pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_CLR_SPEC> {
25 #[allow(clippy::no_effect)]
26 [(); 4][n as usize];
27 CH_TX_END_W::new(self, n * 3)
28 }
29 #[doc = "Bit 0 - Set this bit to clear the CH0_TX_END_INT interrupt."]
30 #[inline(always)]
31 pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
32 CH_TX_END_W::new(self, 0)
33 }
34 #[doc = "Bit 3 - Set this bit to clear the CH1_TX_END_INT interrupt."]
35 #[inline(always)]
36 pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
37 CH_TX_END_W::new(self, 3)
38 }
39 #[doc = "Bit 6 - Set this bit to clear the CH2_TX_END_INT interrupt."]
40 #[inline(always)]
41 pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
42 CH_TX_END_W::new(self, 6)
43 }
44 #[doc = "Bit 9 - Set this bit to clear the CH3_TX_END_INT interrupt."]
45 #[inline(always)]
46 pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
47 CH_TX_END_W::new(self, 9)
48 }
49 #[doc = "Set this bit to clear the CH(0-3)_RX_END_INT interrupt."]
50 #[doc = ""]
51 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_RX_END` field.</div>"]
52 #[inline(always)]
53 pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_CLR_SPEC> {
54 #[allow(clippy::no_effect)]
55 [(); 4][n as usize];
56 CH_RX_END_W::new(self, n * 3 + 1)
57 }
58 #[doc = "Bit 1 - Set this bit to clear the CH0_RX_END_INT interrupt."]
59 #[inline(always)]
60 pub fn ch0_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
61 CH_RX_END_W::new(self, 1)
62 }
63 #[doc = "Bit 4 - Set this bit to clear the CH1_RX_END_INT interrupt."]
64 #[inline(always)]
65 pub fn ch1_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
66 CH_RX_END_W::new(self, 4)
67 }
68 #[doc = "Bit 7 - Set this bit to clear the CH2_RX_END_INT interrupt."]
69 #[inline(always)]
70 pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
71 CH_RX_END_W::new(self, 7)
72 }
73 #[doc = "Bit 10 - Set this bit to clear the CH3_RX_END_INT interrupt."]
74 #[inline(always)]
75 pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
76 CH_RX_END_W::new(self, 10)
77 }
78 #[doc = "Set this bit to clear the CH(0-3)_ERR_INT interrupt."]
79 #[doc = ""]
80 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_ERR` field.</div>"]
81 #[inline(always)]
82 pub fn ch_err(&mut self, n: u8) -> CH_ERR_W<INT_CLR_SPEC> {
83 #[allow(clippy::no_effect)]
84 [(); 4][n as usize];
85 CH_ERR_W::new(self, n * 3 + 2)
86 }
87 #[doc = "Bit 2 - Set this bit to clear the CH0_ERR_INT interrupt."]
88 #[inline(always)]
89 pub fn ch0_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
90 CH_ERR_W::new(self, 2)
91 }
92 #[doc = "Bit 5 - Set this bit to clear the CH1_ERR_INT interrupt."]
93 #[inline(always)]
94 pub fn ch1_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
95 CH_ERR_W::new(self, 5)
96 }
97 #[doc = "Bit 8 - Set this bit to clear the CH2_ERR_INT interrupt."]
98 #[inline(always)]
99 pub fn ch2_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
100 CH_ERR_W::new(self, 8)
101 }
102 #[doc = "Bit 11 - Set this bit to clear the CH3_ERR_INT interrupt."]
103 #[inline(always)]
104 pub fn ch3_err(&mut self) -> CH_ERR_W<INT_CLR_SPEC> {
105 CH_ERR_W::new(self, 11)
106 }
107 #[doc = "Set this bit to clear the CH(0-3)_TX_THR_EVENT_INT interrupt."]
108 #[doc = ""]
109 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
110 #[inline(always)]
111 pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
112 #[allow(clippy::no_effect)]
113 [(); 4][n as usize];
114 CH_TX_THR_EVENT_W::new(self, n + 12)
115 }
116 #[doc = "Bit 12 - Set this bit to clear the CH0_TX_THR_EVENT_INT interrupt."]
117 #[inline(always)]
118 pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
119 CH_TX_THR_EVENT_W::new(self, 12)
120 }
121 #[doc = "Bit 13 - Set this bit to clear the CH1_TX_THR_EVENT_INT interrupt."]
122 #[inline(always)]
123 pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
124 CH_TX_THR_EVENT_W::new(self, 13)
125 }
126 #[doc = "Bit 14 - Set this bit to clear the CH2_TX_THR_EVENT_INT interrupt."]
127 #[inline(always)]
128 pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
129 CH_TX_THR_EVENT_W::new(self, 14)
130 }
131 #[doc = "Bit 15 - Set this bit to clear the CH3_TX_THR_EVENT_INT interrupt."]
132 #[inline(always)]
133 pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
134 CH_TX_THR_EVENT_W::new(self, 15)
135 }
136 #[doc = "Set this bit to clear the CH(0-3)_TX_LOOP_INT interrupt."]
137 #[doc = ""]
138 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
139 #[inline(always)]
140 pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
141 #[allow(clippy::no_effect)]
142 [(); 4][n as usize];
143 CH_TX_LOOP_W::new(self, n + 16)
144 }
145 #[doc = "Bit 16 - Set this bit to clear the CH0_TX_LOOP_INT interrupt."]
146 #[inline(always)]
147 pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
148 CH_TX_LOOP_W::new(self, 16)
149 }
150 #[doc = "Bit 17 - Set this bit to clear the CH1_TX_LOOP_INT interrupt."]
151 #[inline(always)]
152 pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
153 CH_TX_LOOP_W::new(self, 17)
154 }
155 #[doc = "Bit 18 - Set this bit to clear the CH2_TX_LOOP_INT interrupt."]
156 #[inline(always)]
157 pub fn ch2_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
158 CH_TX_LOOP_W::new(self, 18)
159 }
160 #[doc = "Bit 19 - Set this bit to clear the CH3_TX_LOOP_INT interrupt."]
161 #[inline(always)]
162 pub fn ch3_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
163 CH_TX_LOOP_W::new(self, 19)
164 }
165}
166#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct INT_CLR_SPEC;
168impl crate::RegisterSpec for INT_CLR_SPEC {
169 type Ux = u32;
170}
171#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
172impl crate::Writable for INT_CLR_SPEC {
173 type Safety = crate::Unsafe;
174 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
175 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
176}
177#[doc = "`reset()` method sets INT_CLR to value 0"]
178impl crate::Resettable for INT_CLR_SPEC {
179 const RESET_VALUE: u32 = 0;
180}