1#[doc = "Register `TIMING` reader"]
2pub type R = crate::R<TIMING_SPEC>;
3#[doc = "Register `TIMING` writer"]
4pub type W = crate::W<TIMING_SPEC>;
5#[doc = "Field `TX_BCK_IN_DELAY` reader - Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
6pub type TX_BCK_IN_DELAY_R = crate::FieldReader;
7#[doc = "Field `TX_BCK_IN_DELAY` writer - Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
8pub type TX_BCK_IN_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `TX_WS_IN_DELAY` reader - Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
10pub type TX_WS_IN_DELAY_R = crate::FieldReader;
11#[doc = "Field `TX_WS_IN_DELAY` writer - Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
12pub type TX_WS_IN_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `RX_BCK_IN_DELAY` reader - Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
14pub type RX_BCK_IN_DELAY_R = crate::FieldReader;
15#[doc = "Field `RX_BCK_IN_DELAY` writer - Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
16pub type RX_BCK_IN_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `RX_WS_IN_DELAY` reader - Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
18pub type RX_WS_IN_DELAY_R = crate::FieldReader;
19#[doc = "Field `RX_WS_IN_DELAY` writer - Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
20pub type RX_WS_IN_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `RX_SD_IN_DELAY` reader - Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
22pub type RX_SD_IN_DELAY_R = crate::FieldReader;
23#[doc = "Field `RX_SD_IN_DELAY` writer - Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
24pub type RX_SD_IN_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `TX_BCK_OUT_DELAY` reader - Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
26pub type TX_BCK_OUT_DELAY_R = crate::FieldReader;
27#[doc = "Field `TX_BCK_OUT_DELAY` writer - Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
28pub type TX_BCK_OUT_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `TX_WS_OUT_DELAY` reader - Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
30pub type TX_WS_OUT_DELAY_R = crate::FieldReader;
31#[doc = "Field `TX_WS_OUT_DELAY` writer - Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
32pub type TX_WS_OUT_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `TX_SD_OUT_DELAY` reader - Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
34pub type TX_SD_OUT_DELAY_R = crate::FieldReader;
35#[doc = "Field `TX_SD_OUT_DELAY` writer - Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
36pub type TX_SD_OUT_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `RX_WS_OUT_DELAY` reader - Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
38pub type RX_WS_OUT_DELAY_R = crate::FieldReader;
39#[doc = "Field `RX_WS_OUT_DELAY` writer - Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
40pub type RX_WS_OUT_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41#[doc = "Field `RX_BCK_OUT_DELAY` reader - Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
42pub type RX_BCK_OUT_DELAY_R = crate::FieldReader;
43#[doc = "Field `RX_BCK_OUT_DELAY` writer - Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
44pub type RX_BCK_OUT_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
45#[doc = "Field `TX_DSYNC_SW` reader - Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge."]
46pub type TX_DSYNC_SW_R = crate::BitReader;
47#[doc = "Field `TX_DSYNC_SW` writer - Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge."]
48pub type TX_DSYNC_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RX_DSYNC_SW` reader - Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge."]
50pub type RX_DSYNC_SW_R = crate::BitReader;
51#[doc = "Field `RX_DSYNC_SW` writer - Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge."]
52pub type RX_DSYNC_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `DATA_ENABLE_DELAY` reader - Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
54pub type DATA_ENABLE_DELAY_R = crate::FieldReader;
55#[doc = "Field `DATA_ENABLE_DELAY` writer - Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
56pub type DATA_ENABLE_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
57#[doc = "Field `TX_BCK_IN_INV` reader - Set this bit to invert BCK signal input to the slave transmitter."]
58pub type TX_BCK_IN_INV_R = crate::BitReader;
59#[doc = "Field `TX_BCK_IN_INV` writer - Set this bit to invert BCK signal input to the slave transmitter."]
60pub type TX_BCK_IN_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
61impl R {
62 #[doc = "Bits 0:1 - Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
63 #[inline(always)]
64 pub fn tx_bck_in_delay(&self) -> TX_BCK_IN_DELAY_R {
65 TX_BCK_IN_DELAY_R::new((self.bits & 3) as u8)
66 }
67 #[doc = "Bits 2:3 - Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
68 #[inline(always)]
69 pub fn tx_ws_in_delay(&self) -> TX_WS_IN_DELAY_R {
70 TX_WS_IN_DELAY_R::new(((self.bits >> 2) & 3) as u8)
71 }
72 #[doc = "Bits 4:5 - Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
73 #[inline(always)]
74 pub fn rx_bck_in_delay(&self) -> RX_BCK_IN_DELAY_R {
75 RX_BCK_IN_DELAY_R::new(((self.bits >> 4) & 3) as u8)
76 }
77 #[doc = "Bits 6:7 - Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
78 #[inline(always)]
79 pub fn rx_ws_in_delay(&self) -> RX_WS_IN_DELAY_R {
80 RX_WS_IN_DELAY_R::new(((self.bits >> 6) & 3) as u8)
81 }
82 #[doc = "Bits 8:9 - Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
83 #[inline(always)]
84 pub fn rx_sd_in_delay(&self) -> RX_SD_IN_DELAY_R {
85 RX_SD_IN_DELAY_R::new(((self.bits >> 8) & 3) as u8)
86 }
87 #[doc = "Bits 10:11 - Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
88 #[inline(always)]
89 pub fn tx_bck_out_delay(&self) -> TX_BCK_OUT_DELAY_R {
90 TX_BCK_OUT_DELAY_R::new(((self.bits >> 10) & 3) as u8)
91 }
92 #[doc = "Bits 12:13 - Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
93 #[inline(always)]
94 pub fn tx_ws_out_delay(&self) -> TX_WS_OUT_DELAY_R {
95 TX_WS_OUT_DELAY_R::new(((self.bits >> 12) & 3) as u8)
96 }
97 #[doc = "Bits 14:15 - Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
98 #[inline(always)]
99 pub fn tx_sd_out_delay(&self) -> TX_SD_OUT_DELAY_R {
100 TX_SD_OUT_DELAY_R::new(((self.bits >> 14) & 3) as u8)
101 }
102 #[doc = "Bits 16:17 - Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
103 #[inline(always)]
104 pub fn rx_ws_out_delay(&self) -> RX_WS_OUT_DELAY_R {
105 RX_WS_OUT_DELAY_R::new(((self.bits >> 16) & 3) as u8)
106 }
107 #[doc = "Bits 18:19 - Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
108 #[inline(always)]
109 pub fn rx_bck_out_delay(&self) -> RX_BCK_OUT_DELAY_R {
110 RX_BCK_OUT_DELAY_R::new(((self.bits >> 18) & 3) as u8)
111 }
112 #[doc = "Bit 20 - Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge."]
113 #[inline(always)]
114 pub fn tx_dsync_sw(&self) -> TX_DSYNC_SW_R {
115 TX_DSYNC_SW_R::new(((self.bits >> 20) & 1) != 0)
116 }
117 #[doc = "Bit 21 - Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge."]
118 #[inline(always)]
119 pub fn rx_dsync_sw(&self) -> RX_DSYNC_SW_R {
120 RX_DSYNC_SW_R::new(((self.bits >> 21) & 1) != 0)
121 }
122 #[doc = "Bits 22:23 - Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
123 #[inline(always)]
124 pub fn data_enable_delay(&self) -> DATA_ENABLE_DELAY_R {
125 DATA_ENABLE_DELAY_R::new(((self.bits >> 22) & 3) as u8)
126 }
127 #[doc = "Bit 24 - Set this bit to invert BCK signal input to the slave transmitter."]
128 #[inline(always)]
129 pub fn tx_bck_in_inv(&self) -> TX_BCK_IN_INV_R {
130 TX_BCK_IN_INV_R::new(((self.bits >> 24) & 1) != 0)
131 }
132}
133#[cfg(feature = "impl-register-debug")]
134impl core::fmt::Debug for R {
135 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
136 f.debug_struct("TIMING")
137 .field("tx_bck_in_delay", &self.tx_bck_in_delay())
138 .field("tx_ws_in_delay", &self.tx_ws_in_delay())
139 .field("rx_bck_in_delay", &self.rx_bck_in_delay())
140 .field("rx_ws_in_delay", &self.rx_ws_in_delay())
141 .field("rx_sd_in_delay", &self.rx_sd_in_delay())
142 .field("tx_bck_out_delay", &self.tx_bck_out_delay())
143 .field("tx_ws_out_delay", &self.tx_ws_out_delay())
144 .field("tx_sd_out_delay", &self.tx_sd_out_delay())
145 .field("rx_ws_out_delay", &self.rx_ws_out_delay())
146 .field("rx_bck_out_delay", &self.rx_bck_out_delay())
147 .field("tx_dsync_sw", &self.tx_dsync_sw())
148 .field("rx_dsync_sw", &self.rx_dsync_sw())
149 .field("data_enable_delay", &self.data_enable_delay())
150 .field("tx_bck_in_inv", &self.tx_bck_in_inv())
151 .finish()
152 }
153}
154impl W {
155 #[doc = "Bits 0:1 - Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
156 #[inline(always)]
157 pub fn tx_bck_in_delay(&mut self) -> TX_BCK_IN_DELAY_W<TIMING_SPEC> {
158 TX_BCK_IN_DELAY_W::new(self, 0)
159 }
160 #[doc = "Bits 2:3 - Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
161 #[inline(always)]
162 pub fn tx_ws_in_delay(&mut self) -> TX_WS_IN_DELAY_W<TIMING_SPEC> {
163 TX_WS_IN_DELAY_W::new(self, 2)
164 }
165 #[doc = "Bits 4:5 - Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
166 #[inline(always)]
167 pub fn rx_bck_in_delay(&mut self) -> RX_BCK_IN_DELAY_W<TIMING_SPEC> {
168 RX_BCK_IN_DELAY_W::new(self, 4)
169 }
170 #[doc = "Bits 6:7 - Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
171 #[inline(always)]
172 pub fn rx_ws_in_delay(&mut self) -> RX_WS_IN_DELAY_W<TIMING_SPEC> {
173 RX_WS_IN_DELAY_W::new(self, 6)
174 }
175 #[doc = "Bits 8:9 - Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
176 #[inline(always)]
177 pub fn rx_sd_in_delay(&mut self) -> RX_SD_IN_DELAY_W<TIMING_SPEC> {
178 RX_SD_IN_DELAY_W::new(self, 8)
179 }
180 #[doc = "Bits 10:11 - Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
181 #[inline(always)]
182 pub fn tx_bck_out_delay(&mut self) -> TX_BCK_OUT_DELAY_W<TIMING_SPEC> {
183 TX_BCK_OUT_DELAY_W::new(self, 10)
184 }
185 #[doc = "Bits 12:13 - Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
186 #[inline(always)]
187 pub fn tx_ws_out_delay(&mut self) -> TX_WS_OUT_DELAY_W<TIMING_SPEC> {
188 TX_WS_OUT_DELAY_W::new(self, 12)
189 }
190 #[doc = "Bits 14:15 - Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
191 #[inline(always)]
192 pub fn tx_sd_out_delay(&mut self) -> TX_SD_OUT_DELAY_W<TIMING_SPEC> {
193 TX_SD_OUT_DELAY_W::new(self, 14)
194 }
195 #[doc = "Bits 16:17 - Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
196 #[inline(always)]
197 pub fn rx_ws_out_delay(&mut self) -> RX_WS_OUT_DELAY_W<TIMING_SPEC> {
198 RX_WS_OUT_DELAY_W::new(self, 16)
199 }
200 #[doc = "Bits 18:19 - Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles."]
201 #[inline(always)]
202 pub fn rx_bck_out_delay(&mut self) -> RX_BCK_OUT_DELAY_W<TIMING_SPEC> {
203 RX_BCK_OUT_DELAY_W::new(self, 18)
204 }
205 #[doc = "Bit 20 - Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge."]
206 #[inline(always)]
207 pub fn tx_dsync_sw(&mut self) -> TX_DSYNC_SW_W<TIMING_SPEC> {
208 TX_DSYNC_SW_W::new(self, 20)
209 }
210 #[doc = "Bit 21 - Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge."]
211 #[inline(always)]
212 pub fn rx_dsync_sw(&mut self) -> RX_DSYNC_SW_W<TIMING_SPEC> {
213 RX_DSYNC_SW_W::new(self, 21)
214 }
215 #[doc = "Bits 22:23 - Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
216 #[inline(always)]
217 pub fn data_enable_delay(&mut self) -> DATA_ENABLE_DELAY_W<TIMING_SPEC> {
218 DATA_ENABLE_DELAY_W::new(self, 22)
219 }
220 #[doc = "Bit 24 - Set this bit to invert BCK signal input to the slave transmitter."]
221 #[inline(always)]
222 pub fn tx_bck_in_inv(&mut self) -> TX_BCK_IN_INV_W<TIMING_SPEC> {
223 TX_BCK_IN_INV_W::new(self, 24)
224 }
225}
226#[doc = "I2S timing register\n\nYou can [`read`](crate::Reg::read) this register and get [`timing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
227pub struct TIMING_SPEC;
228impl crate::RegisterSpec for TIMING_SPEC {
229 type Ux = u32;
230}
231#[doc = "`read()` method returns [`timing::R`](R) reader structure"]
232impl crate::Readable for TIMING_SPEC {}
233#[doc = "`write(|w| ..)` method takes [`timing::W`](W) writer structure"]
234impl crate::Writable for TIMING_SPEC {
235 type Safety = crate::Unsafe;
236 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
237 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
238}
239#[doc = "`reset()` method sets TIMING to value 0"]
240impl crate::Resettable for TIMING_SPEC {
241 const RESET_VALUE: u32 = 0;
242}