1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `RXFIFO_FULL` writer - Set this bit to clear UART_THE RXFIFO_FULL_INT interrupt."]
4pub type RXFIFO_FULL_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TXFIFO_EMPTY` writer - Set this bit to clear UART_TXFIFO_EMPTY_INT interrupt."]
6pub type TXFIFO_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `PARITY_ERR` writer - Set this bit to clear UART_PARITY_ERR_INT interrupt."]
8pub type PARITY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `FRM_ERR` writer - Set this bit to clear UART_FRM_ERR_INT interrupt."]
10pub type FRM_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `RXFIFO_OVF` writer - Set this bit to clear UART_UART_RXFIFO_OVF_INT interrupt."]
12pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `DSR_CHG` writer - Set this bit to clear UART_DSR_CHG_INT interrupt."]
14pub type DSR_CHG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `CTS_CHG` writer - Set this bit to clear UART_CTS_CHG_INT interrupt."]
16pub type CTS_CHG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `BRK_DET` writer - Set this bit to clear UART_BRK_DET_INT interrupt."]
18pub type BRK_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `RXFIFO_TOUT` writer - Set this bit to clear UART_RXFIFO_TOUT_INT interrupt."]
20pub type RXFIFO_TOUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `SW_XON` writer - Set this bit to clear UART_SW_XON_INT interrupt."]
22pub type SW_XON_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `SW_XOFF` writer - Set this bit to clear UART_SW_XOFF_INT interrupt."]
24pub type SW_XOFF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `GLITCH_DET` writer - Set this bit to clear UART_GLITCH_DET_INT interrupt."]
26pub type GLITCH_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `TX_BRK_DONE` writer - Set this bit to clear UART_TX_BRK_DONE_INT interrupt."]
28pub type TX_BRK_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `TX_BRK_IDLE_DONE` writer - Set this bit to clear UART_TX_BRK_IDLE_DONE_INT interrupt."]
30pub type TX_BRK_IDLE_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `TX_DONE` writer - Set this bit to clear UART_TX_DONE_INT interrupt."]
32pub type TX_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `RS485_PARITY_ERR` writer - Set this bit to clear UART_RS485_PARITY_ERR_INT interrupt."]
34pub type RS485_PARITY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `RS485_FRM_ERR` writer - Set this bit to clear UART_RS485_FRM_ERR_INT interrupt."]
36pub type RS485_FRM_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `RS485_CLASH` writer - Set this bit to clear UART_RS485_CLASH_INT interrupt."]
38pub type RS485_CLASH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `AT_CMD_CHAR_DET` writer - Set this bit to clear UART_AT_CMD_CHAR_DET_INT interrupt."]
40pub type AT_CMD_CHAR_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `WAKEUP` writer - Set this bit to clear UART_WAKEUP_INT interrupt."]
42pub type WAKEUP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
45 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
46 write!(f, "(not readable)")
47 }
48}
49impl W {
50 #[doc = "Bit 0 - Set this bit to clear UART_THE RXFIFO_FULL_INT interrupt."]
51 #[inline(always)]
52 pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_CLR_SPEC> {
53 RXFIFO_FULL_W::new(self, 0)
54 }
55 #[doc = "Bit 1 - Set this bit to clear UART_TXFIFO_EMPTY_INT interrupt."]
56 #[inline(always)]
57 pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_CLR_SPEC> {
58 TXFIFO_EMPTY_W::new(self, 1)
59 }
60 #[doc = "Bit 2 - Set this bit to clear UART_PARITY_ERR_INT interrupt."]
61 #[inline(always)]
62 pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_CLR_SPEC> {
63 PARITY_ERR_W::new(self, 2)
64 }
65 #[doc = "Bit 3 - Set this bit to clear UART_FRM_ERR_INT interrupt."]
66 #[inline(always)]
67 pub fn frm_err(&mut self) -> FRM_ERR_W<INT_CLR_SPEC> {
68 FRM_ERR_W::new(self, 3)
69 }
70 #[doc = "Bit 4 - Set this bit to clear UART_UART_RXFIFO_OVF_INT interrupt."]
71 #[inline(always)]
72 pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
73 RXFIFO_OVF_W::new(self, 4)
74 }
75 #[doc = "Bit 5 - Set this bit to clear UART_DSR_CHG_INT interrupt."]
76 #[inline(always)]
77 pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_CLR_SPEC> {
78 DSR_CHG_W::new(self, 5)
79 }
80 #[doc = "Bit 6 - Set this bit to clear UART_CTS_CHG_INT interrupt."]
81 #[inline(always)]
82 pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_CLR_SPEC> {
83 CTS_CHG_W::new(self, 6)
84 }
85 #[doc = "Bit 7 - Set this bit to clear UART_BRK_DET_INT interrupt."]
86 #[inline(always)]
87 pub fn brk_det(&mut self) -> BRK_DET_W<INT_CLR_SPEC> {
88 BRK_DET_W::new(self, 7)
89 }
90 #[doc = "Bit 8 - Set this bit to clear UART_RXFIFO_TOUT_INT interrupt."]
91 #[inline(always)]
92 pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_CLR_SPEC> {
93 RXFIFO_TOUT_W::new(self, 8)
94 }
95 #[doc = "Bit 9 - Set this bit to clear UART_SW_XON_INT interrupt."]
96 #[inline(always)]
97 pub fn sw_xon(&mut self) -> SW_XON_W<INT_CLR_SPEC> {
98 SW_XON_W::new(self, 9)
99 }
100 #[doc = "Bit 10 - Set this bit to clear UART_SW_XOFF_INT interrupt."]
101 #[inline(always)]
102 pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_CLR_SPEC> {
103 SW_XOFF_W::new(self, 10)
104 }
105 #[doc = "Bit 11 - Set this bit to clear UART_GLITCH_DET_INT interrupt."]
106 #[inline(always)]
107 pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
108 GLITCH_DET_W::new(self, 11)
109 }
110 #[doc = "Bit 12 - Set this bit to clear UART_TX_BRK_DONE_INT interrupt."]
111 #[inline(always)]
112 pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_CLR_SPEC> {
113 TX_BRK_DONE_W::new(self, 12)
114 }
115 #[doc = "Bit 13 - Set this bit to clear UART_TX_BRK_IDLE_DONE_INT interrupt."]
116 #[inline(always)]
117 pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_CLR_SPEC> {
118 TX_BRK_IDLE_DONE_W::new(self, 13)
119 }
120 #[doc = "Bit 14 - Set this bit to clear UART_TX_DONE_INT interrupt."]
121 #[inline(always)]
122 pub fn tx_done(&mut self) -> TX_DONE_W<INT_CLR_SPEC> {
123 TX_DONE_W::new(self, 14)
124 }
125 #[doc = "Bit 15 - Set this bit to clear UART_RS485_PARITY_ERR_INT interrupt."]
126 #[inline(always)]
127 pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_CLR_SPEC> {
128 RS485_PARITY_ERR_W::new(self, 15)
129 }
130 #[doc = "Bit 16 - Set this bit to clear UART_RS485_FRM_ERR_INT interrupt."]
131 #[inline(always)]
132 pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_CLR_SPEC> {
133 RS485_FRM_ERR_W::new(self, 16)
134 }
135 #[doc = "Bit 17 - Set this bit to clear UART_RS485_CLASH_INT interrupt."]
136 #[inline(always)]
137 pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_CLR_SPEC> {
138 RS485_CLASH_W::new(self, 17)
139 }
140 #[doc = "Bit 18 - Set this bit to clear UART_AT_CMD_CHAR_DET_INT interrupt."]
141 #[inline(always)]
142 pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_CLR_SPEC> {
143 AT_CMD_CHAR_DET_W::new(self, 18)
144 }
145 #[doc = "Bit 19 - Set this bit to clear UART_WAKEUP_INT interrupt."]
146 #[inline(always)]
147 pub fn wakeup(&mut self) -> WAKEUP_W<INT_CLR_SPEC> {
148 WAKEUP_W::new(self, 19)
149 }
150}
151#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct INT_CLR_SPEC;
153impl crate::RegisterSpec for INT_CLR_SPEC {
154 type Ux = u32;
155}
156#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
157impl crate::Writable for INT_CLR_SPEC {
158 type Safety = crate::Unsafe;
159 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
160 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x000f_ffff;
161}
162#[doc = "`reset()` method sets INT_CLR to value 0"]
163impl crate::Resettable for INT_CLR_SPEC {
164 const RESET_VALUE: u32 = 0;
165}