esp32s2/system/
sysclk_conf.rs

1#[doc = "Register `SYSCLK_CONF` reader"]
2pub type R = crate::R<SYSCLK_CONF_SPEC>;
3#[doc = "Register `SYSCLK_CONF` writer"]
4pub type W = crate::W<SYSCLK_CONF_SPEC>;
5#[doc = "Field `PRE_DIV_CNT` reader - This field is used to set the count of prescaler of XTAL\\_CLK."]
6pub type PRE_DIV_CNT_R = crate::FieldReader<u16>;
7#[doc = "Field `PRE_DIV_CNT` writer - This field is used to set the count of prescaler of XTAL\\_CLK."]
8pub type PRE_DIV_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
9#[doc = "Field `SOC_CLK_SEL` reader - This field is used to select SOC clock."]
10pub type SOC_CLK_SEL_R = crate::FieldReader;
11#[doc = "Field `SOC_CLK_SEL` writer - This field is used to select SOC clock."]
12pub type SOC_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `CLK_XTAL_FREQ` reader - This field is used to read XTAL frequency in MHz."]
14pub type CLK_XTAL_FREQ_R = crate::FieldReader;
15#[doc = "Field `CLK_DIV_EN` reader - Not used, extends from ESP32."]
16pub type CLK_DIV_EN_R = crate::BitReader;
17impl R {
18    #[doc = "Bits 0:9 - This field is used to set the count of prescaler of XTAL\\_CLK."]
19    #[inline(always)]
20    pub fn pre_div_cnt(&self) -> PRE_DIV_CNT_R {
21        PRE_DIV_CNT_R::new((self.bits & 0x03ff) as u16)
22    }
23    #[doc = "Bits 10:11 - This field is used to select SOC clock."]
24    #[inline(always)]
25    pub fn soc_clk_sel(&self) -> SOC_CLK_SEL_R {
26        SOC_CLK_SEL_R::new(((self.bits >> 10) & 3) as u8)
27    }
28    #[doc = "Bits 12:18 - This field is used to read XTAL frequency in MHz."]
29    #[inline(always)]
30    pub fn clk_xtal_freq(&self) -> CLK_XTAL_FREQ_R {
31        CLK_XTAL_FREQ_R::new(((self.bits >> 12) & 0x7f) as u8)
32    }
33    #[doc = "Bit 19 - Not used, extends from ESP32."]
34    #[inline(always)]
35    pub fn clk_div_en(&self) -> CLK_DIV_EN_R {
36        CLK_DIV_EN_R::new(((self.bits >> 19) & 1) != 0)
37    }
38}
39#[cfg(feature = "impl-register-debug")]
40impl core::fmt::Debug for R {
41    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
42        f.debug_struct("SYSCLK_CONF")
43            .field("pre_div_cnt", &self.pre_div_cnt())
44            .field("soc_clk_sel", &self.soc_clk_sel())
45            .field("clk_xtal_freq", &self.clk_xtal_freq())
46            .field("clk_div_en", &self.clk_div_en())
47            .finish()
48    }
49}
50impl W {
51    #[doc = "Bits 0:9 - This field is used to set the count of prescaler of XTAL\\_CLK."]
52    #[inline(always)]
53    pub fn pre_div_cnt(&mut self) -> PRE_DIV_CNT_W<SYSCLK_CONF_SPEC> {
54        PRE_DIV_CNT_W::new(self, 0)
55    }
56    #[doc = "Bits 10:11 - This field is used to select SOC clock."]
57    #[inline(always)]
58    pub fn soc_clk_sel(&mut self) -> SOC_CLK_SEL_W<SYSCLK_CONF_SPEC> {
59        SOC_CLK_SEL_W::new(self, 10)
60    }
61}
62#[doc = "SoC clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`sysclk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysclk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
63pub struct SYSCLK_CONF_SPEC;
64impl crate::RegisterSpec for SYSCLK_CONF_SPEC {
65    type Ux = u32;
66}
67#[doc = "`read()` method returns [`sysclk_conf::R`](R) reader structure"]
68impl crate::Readable for SYSCLK_CONF_SPEC {}
69#[doc = "`write(|w| ..)` method takes [`sysclk_conf::W`](W) writer structure"]
70impl crate::Writable for SYSCLK_CONF_SPEC {
71    type Safety = crate::Unsafe;
72    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
74}
75#[doc = "`reset()` method sets SYSCLK_CONF to value 0x01"]
76impl crate::Resettable for SYSCLK_CONF_SPEC {
77    const RESET_VALUE: u32 = 0x01;
78}
esp32s2/system/sysclk_conf.rs

esp32s2/system/
sysclk_conf.rs
