1#[doc = "Register `USER` reader"]
2pub type R = crate::R<USER_SPEC>;
3#[doc = "Register `USER` writer"]
4pub type W = crate::W<USER_SPEC>;
5#[doc = "Field `DOUTDIN` reader - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
6pub type DOUTDIN_R = crate::BitReader;
7#[doc = "Field `DOUTDIN` writer - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
8pub type DOUTDIN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `QPI_MODE` reader - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
10pub type QPI_MODE_R = crate::BitReader;
11#[doc = "Field `QPI_MODE` writer - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
12pub type QPI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OPI_MODE` reader - Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state."]
14pub type OPI_MODE_R = crate::BitReader;
15#[doc = "Field `OPI_MODE` writer - Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state."]
16pub type OPI_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
18pub type TSCK_I_EDGE_R = crate::BitReader;
19#[doc = "Field `TSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
20pub type TSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CS_HOLD` reader - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
22pub type CS_HOLD_R = crate::BitReader;
23#[doc = "Field `CS_HOLD` writer - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
24pub type CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CS_SETUP` reader - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
26pub type CS_SETUP_R = crate::BitReader;
27#[doc = "Field `CS_SETUP` writer - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
28pub type CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RSCK_I_EDGE` reader - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
30pub type RSCK_I_EDGE_R = crate::BitReader;
31#[doc = "Field `RSCK_I_EDGE` writer - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
32pub type RSCK_I_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CK_OUT_EDGE` reader - the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state."]
34pub type CK_OUT_EDGE_R = crate::BitReader;
35#[doc = "Field `CK_OUT_EDGE` writer - the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state."]
36pub type CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `RD_BYTE_ORDER` reader - In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state."]
38pub type RD_BYTE_ORDER_R = crate::BitReader;
39#[doc = "Field `RD_BYTE_ORDER` writer - In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state."]
40pub type RD_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `WR_BYTE_ORDER` reader - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state."]
42pub type WR_BYTE_ORDER_R = crate::BitReader;
43#[doc = "Field `WR_BYTE_ORDER` writer - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state."]
44pub type WR_BYTE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FWRITE_DUAL` reader - In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state."]
46pub type FWRITE_DUAL_R = crate::BitReader;
47#[doc = "Field `FWRITE_DUAL` writer - In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state."]
48pub type FWRITE_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `FWRITE_QUAD` reader - In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state."]
50pub type FWRITE_QUAD_R = crate::BitReader;
51#[doc = "Field `FWRITE_QUAD` writer - In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state."]
52pub type FWRITE_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `FWRITE_OCT` reader - In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state."]
54pub type FWRITE_OCT_R = crate::BitReader;
55#[doc = "Field `FWRITE_OCT` writer - In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state."]
56pub type FWRITE_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `USR_CONF_NXT` reader - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
58pub type USR_CONF_NXT_R = crate::BitReader;
59#[doc = "Field `USR_CONF_NXT` writer - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
60pub type USR_CONF_NXT_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `SIO` reader - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
62pub type SIO_R = crate::BitReader;
63#[doc = "Field `SIO` writer - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
64pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `USR_HOLD_POL` reader - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state."]
66pub type USR_HOLD_POL_R = crate::BitReader;
67#[doc = "Field `USR_HOLD_POL` writer - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state."]
68pub type USR_HOLD_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `USR_DOUT_HOLD` reader - spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
70pub type USR_DOUT_HOLD_R = crate::BitReader;
71#[doc = "Field `USR_DOUT_HOLD` writer - spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
72pub type USR_DOUT_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `USR_DIN_HOLD` reader - spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
74pub type USR_DIN_HOLD_R = crate::BitReader;
75#[doc = "Field `USR_DIN_HOLD` writer - spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
76pub type USR_DIN_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `USR_DUMMY_HOLD` reader - spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
78pub type USR_DUMMY_HOLD_R = crate::BitReader;
79#[doc = "Field `USR_DUMMY_HOLD` writer - spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
80pub type USR_DUMMY_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `USR_ADDR_HOLD` reader - spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
82pub type USR_ADDR_HOLD_R = crate::BitReader;
83#[doc = "Field `USR_ADDR_HOLD` writer - spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
84pub type USR_ADDR_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `USR_CMD_HOLD` reader - spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
86pub type USR_CMD_HOLD_R = crate::BitReader;
87#[doc = "Field `USR_CMD_HOLD` writer - spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
88pub type USR_CMD_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `USR_PREP_HOLD` reader - spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
90pub type USR_PREP_HOLD_R = crate::BitReader;
91#[doc = "Field `USR_PREP_HOLD` writer - spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
92pub type USR_PREP_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `USR_MISO_HIGHPART` reader - read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state."]
94pub type USR_MISO_HIGHPART_R = crate::BitReader;
95#[doc = "Field `USR_MISO_HIGHPART` writer - read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state."]
96pub type USR_MISO_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `USR_MOSI_HIGHPART` reader - write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state."]
98pub type USR_MOSI_HIGHPART_R = crate::BitReader;
99#[doc = "Field `USR_MOSI_HIGHPART` writer - write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state."]
100pub type USR_MOSI_HIGHPART_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `USR_DUMMY_IDLE` reader - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
102pub type USR_DUMMY_IDLE_R = crate::BitReader;
103#[doc = "Field `USR_DUMMY_IDLE` writer - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
104pub type USR_DUMMY_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `USR_MOSI` reader - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
106pub type USR_MOSI_R = crate::BitReader;
107#[doc = "Field `USR_MOSI` writer - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
108pub type USR_MOSI_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `USR_MISO` reader - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
110pub type USR_MISO_R = crate::BitReader;
111#[doc = "Field `USR_MISO` writer - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
112pub type USR_MISO_W<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `USR_DUMMY` reader - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
114pub type USR_DUMMY_R = crate::BitReader;
115#[doc = "Field `USR_DUMMY` writer - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
116pub type USR_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
117#[doc = "Field `USR_ADDR` reader - This bit enable the address phase of an operation. Can be configured in CONF state."]
118pub type USR_ADDR_R = crate::BitReader;
119#[doc = "Field `USR_ADDR` writer - This bit enable the address phase of an operation. Can be configured in CONF state."]
120pub type USR_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
121#[doc = "Field `USR_COMMAND` reader - This bit enable the command phase of an operation. Can be configured in CONF state."]
122pub type USR_COMMAND_R = crate::BitReader;
123#[doc = "Field `USR_COMMAND` writer - This bit enable the command phase of an operation. Can be configured in CONF state."]
124pub type USR_COMMAND_W<'a, REG> = crate::BitWriter<'a, REG>;
125impl R {
126 #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
127 #[inline(always)]
128 pub fn doutdin(&self) -> DOUTDIN_R {
129 DOUTDIN_R::new((self.bits & 1) != 0)
130 }
131 #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
132 #[inline(always)]
133 pub fn qpi_mode(&self) -> QPI_MODE_R {
134 QPI_MODE_R::new(((self.bits >> 3) & 1) != 0)
135 }
136 #[doc = "Bit 4 - Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state."]
137 #[inline(always)]
138 pub fn opi_mode(&self) -> OPI_MODE_R {
139 OPI_MODE_R::new(((self.bits >> 4) & 1) != 0)
140 }
141 #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
142 #[inline(always)]
143 pub fn tsck_i_edge(&self) -> TSCK_I_EDGE_R {
144 TSCK_I_EDGE_R::new(((self.bits >> 5) & 1) != 0)
145 }
146 #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
147 #[inline(always)]
148 pub fn cs_hold(&self) -> CS_HOLD_R {
149 CS_HOLD_R::new(((self.bits >> 6) & 1) != 0)
150 }
151 #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
152 #[inline(always)]
153 pub fn cs_setup(&self) -> CS_SETUP_R {
154 CS_SETUP_R::new(((self.bits >> 7) & 1) != 0)
155 }
156 #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
157 #[inline(always)]
158 pub fn rsck_i_edge(&self) -> RSCK_I_EDGE_R {
159 RSCK_I_EDGE_R::new(((self.bits >> 8) & 1) != 0)
160 }
161 #[doc = "Bit 9 - the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state."]
162 #[inline(always)]
163 pub fn ck_out_edge(&self) -> CK_OUT_EDGE_R {
164 CK_OUT_EDGE_R::new(((self.bits >> 9) & 1) != 0)
165 }
166 #[doc = "Bit 10 - In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state."]
167 #[inline(always)]
168 pub fn rd_byte_order(&self) -> RD_BYTE_ORDER_R {
169 RD_BYTE_ORDER_R::new(((self.bits >> 10) & 1) != 0)
170 }
171 #[doc = "Bit 11 - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state."]
172 #[inline(always)]
173 pub fn wr_byte_order(&self) -> WR_BYTE_ORDER_R {
174 WR_BYTE_ORDER_R::new(((self.bits >> 11) & 1) != 0)
175 }
176 #[doc = "Bit 12 - In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state."]
177 #[inline(always)]
178 pub fn fwrite_dual(&self) -> FWRITE_DUAL_R {
179 FWRITE_DUAL_R::new(((self.bits >> 12) & 1) != 0)
180 }
181 #[doc = "Bit 13 - In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state."]
182 #[inline(always)]
183 pub fn fwrite_quad(&self) -> FWRITE_QUAD_R {
184 FWRITE_QUAD_R::new(((self.bits >> 13) & 1) != 0)
185 }
186 #[doc = "Bit 14 - In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state."]
187 #[inline(always)]
188 pub fn fwrite_oct(&self) -> FWRITE_OCT_R {
189 FWRITE_OCT_R::new(((self.bits >> 14) & 1) != 0)
190 }
191 #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
192 #[inline(always)]
193 pub fn usr_conf_nxt(&self) -> USR_CONF_NXT_R {
194 USR_CONF_NXT_R::new(((self.bits >> 15) & 1) != 0)
195 }
196 #[doc = "Bit 16 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
197 #[inline(always)]
198 pub fn sio(&self) -> SIO_R {
199 SIO_R::new(((self.bits >> 16) & 1) != 0)
200 }
201 #[doc = "Bit 17 - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state."]
202 #[inline(always)]
203 pub fn usr_hold_pol(&self) -> USR_HOLD_POL_R {
204 USR_HOLD_POL_R::new(((self.bits >> 17) & 1) != 0)
205 }
206 #[doc = "Bit 18 - spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
207 #[inline(always)]
208 pub fn usr_dout_hold(&self) -> USR_DOUT_HOLD_R {
209 USR_DOUT_HOLD_R::new(((self.bits >> 18) & 1) != 0)
210 }
211 #[doc = "Bit 19 - spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
212 #[inline(always)]
213 pub fn usr_din_hold(&self) -> USR_DIN_HOLD_R {
214 USR_DIN_HOLD_R::new(((self.bits >> 19) & 1) != 0)
215 }
216 #[doc = "Bit 20 - spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
217 #[inline(always)]
218 pub fn usr_dummy_hold(&self) -> USR_DUMMY_HOLD_R {
219 USR_DUMMY_HOLD_R::new(((self.bits >> 20) & 1) != 0)
220 }
221 #[doc = "Bit 21 - spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
222 #[inline(always)]
223 pub fn usr_addr_hold(&self) -> USR_ADDR_HOLD_R {
224 USR_ADDR_HOLD_R::new(((self.bits >> 21) & 1) != 0)
225 }
226 #[doc = "Bit 22 - spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
227 #[inline(always)]
228 pub fn usr_cmd_hold(&self) -> USR_CMD_HOLD_R {
229 USR_CMD_HOLD_R::new(((self.bits >> 22) & 1) != 0)
230 }
231 #[doc = "Bit 23 - spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
232 #[inline(always)]
233 pub fn usr_prep_hold(&self) -> USR_PREP_HOLD_R {
234 USR_PREP_HOLD_R::new(((self.bits >> 23) & 1) != 0)
235 }
236 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state."]
237 #[inline(always)]
238 pub fn usr_miso_highpart(&self) -> USR_MISO_HIGHPART_R {
239 USR_MISO_HIGHPART_R::new(((self.bits >> 24) & 1) != 0)
240 }
241 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state."]
242 #[inline(always)]
243 pub fn usr_mosi_highpart(&self) -> USR_MOSI_HIGHPART_R {
244 USR_MOSI_HIGHPART_R::new(((self.bits >> 25) & 1) != 0)
245 }
246 #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
247 #[inline(always)]
248 pub fn usr_dummy_idle(&self) -> USR_DUMMY_IDLE_R {
249 USR_DUMMY_IDLE_R::new(((self.bits >> 26) & 1) != 0)
250 }
251 #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
252 #[inline(always)]
253 pub fn usr_mosi(&self) -> USR_MOSI_R {
254 USR_MOSI_R::new(((self.bits >> 27) & 1) != 0)
255 }
256 #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
257 #[inline(always)]
258 pub fn usr_miso(&self) -> USR_MISO_R {
259 USR_MISO_R::new(((self.bits >> 28) & 1) != 0)
260 }
261 #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
262 #[inline(always)]
263 pub fn usr_dummy(&self) -> USR_DUMMY_R {
264 USR_DUMMY_R::new(((self.bits >> 29) & 1) != 0)
265 }
266 #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."]
267 #[inline(always)]
268 pub fn usr_addr(&self) -> USR_ADDR_R {
269 USR_ADDR_R::new(((self.bits >> 30) & 1) != 0)
270 }
271 #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."]
272 #[inline(always)]
273 pub fn usr_command(&self) -> USR_COMMAND_R {
274 USR_COMMAND_R::new(((self.bits >> 31) & 1) != 0)
275 }
276}
277#[cfg(feature = "impl-register-debug")]
278impl core::fmt::Debug for R {
279 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
280 f.debug_struct("USER")
281 .field("doutdin", &self.doutdin())
282 .field("qpi_mode", &self.qpi_mode())
283 .field("opi_mode", &self.opi_mode())
284 .field("tsck_i_edge", &self.tsck_i_edge())
285 .field("cs_hold", &self.cs_hold())
286 .field("cs_setup", &self.cs_setup())
287 .field("rsck_i_edge", &self.rsck_i_edge())
288 .field("ck_out_edge", &self.ck_out_edge())
289 .field("rd_byte_order", &self.rd_byte_order())
290 .field("wr_byte_order", &self.wr_byte_order())
291 .field("fwrite_dual", &self.fwrite_dual())
292 .field("fwrite_quad", &self.fwrite_quad())
293 .field("fwrite_oct", &self.fwrite_oct())
294 .field("usr_conf_nxt", &self.usr_conf_nxt())
295 .field("sio", &self.sio())
296 .field("usr_hold_pol", &self.usr_hold_pol())
297 .field("usr_dout_hold", &self.usr_dout_hold())
298 .field("usr_din_hold", &self.usr_din_hold())
299 .field("usr_dummy_hold", &self.usr_dummy_hold())
300 .field("usr_addr_hold", &self.usr_addr_hold())
301 .field("usr_cmd_hold", &self.usr_cmd_hold())
302 .field("usr_prep_hold", &self.usr_prep_hold())
303 .field("usr_miso_highpart", &self.usr_miso_highpart())
304 .field("usr_mosi_highpart", &self.usr_mosi_highpart())
305 .field("usr_dummy_idle", &self.usr_dummy_idle())
306 .field("usr_mosi", &self.usr_mosi())
307 .field("usr_miso", &self.usr_miso())
308 .field("usr_dummy", &self.usr_dummy())
309 .field("usr_addr", &self.usr_addr())
310 .field("usr_command", &self.usr_command())
311 .finish()
312 }
313}
314impl W {
315 #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
316 #[inline(always)]
317 pub fn doutdin(&mut self) -> DOUTDIN_W<USER_SPEC> {
318 DOUTDIN_W::new(self, 0)
319 }
320 #[doc = "Bit 3 - Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state."]
321 #[inline(always)]
322 pub fn qpi_mode(&mut self) -> QPI_MODE_W<USER_SPEC> {
323 QPI_MODE_W::new(self, 3)
324 }
325 #[doc = "Bit 4 - Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state."]
326 #[inline(always)]
327 pub fn opi_mode(&mut self) -> OPI_MODE_W<USER_SPEC> {
328 OPI_MODE_W::new(self, 4)
329 }
330 #[doc = "Bit 5 - In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i."]
331 #[inline(always)]
332 pub fn tsck_i_edge(&mut self) -> TSCK_I_EDGE_W<USER_SPEC> {
333 TSCK_I_EDGE_W::new(self, 5)
334 }
335 #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state."]
336 #[inline(always)]
337 pub fn cs_hold(&mut self) -> CS_HOLD_W<USER_SPEC> {
338 CS_HOLD_W::new(self, 6)
339 }
340 #[doc = "Bit 7 - spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state."]
341 #[inline(always)]
342 pub fn cs_setup(&mut self) -> CS_SETUP_W<USER_SPEC> {
343 CS_SETUP_W::new(self, 7)
344 }
345 #[doc = "Bit 8 - In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i."]
346 #[inline(always)]
347 pub fn rsck_i_edge(&mut self) -> RSCK_I_EDGE_W<USER_SPEC> {
348 RSCK_I_EDGE_W::new(self, 8)
349 }
350 #[doc = "Bit 9 - the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state."]
351 #[inline(always)]
352 pub fn ck_out_edge(&mut self) -> CK_OUT_EDGE_W<USER_SPEC> {
353 CK_OUT_EDGE_W::new(self, 9)
354 }
355 #[doc = "Bit 10 - In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state."]
356 #[inline(always)]
357 pub fn rd_byte_order(&mut self) -> RD_BYTE_ORDER_W<USER_SPEC> {
358 RD_BYTE_ORDER_W::new(self, 10)
359 }
360 #[doc = "Bit 11 - In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state."]
361 #[inline(always)]
362 pub fn wr_byte_order(&mut self) -> WR_BYTE_ORDER_W<USER_SPEC> {
363 WR_BYTE_ORDER_W::new(self, 11)
364 }
365 #[doc = "Bit 12 - In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state."]
366 #[inline(always)]
367 pub fn fwrite_dual(&mut self) -> FWRITE_DUAL_W<USER_SPEC> {
368 FWRITE_DUAL_W::new(self, 12)
369 }
370 #[doc = "Bit 13 - In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state."]
371 #[inline(always)]
372 pub fn fwrite_quad(&mut self) -> FWRITE_QUAD_W<USER_SPEC> {
373 FWRITE_QUAD_W::new(self, 13)
374 }
375 #[doc = "Bit 14 - In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state."]
376 #[inline(always)]
377 pub fn fwrite_oct(&mut self) -> FWRITE_OCT_W<USER_SPEC> {
378 FWRITE_OCT_W::new(self, 14)
379 }
380 #[doc = "Bit 15 - 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state."]
381 #[inline(always)]
382 pub fn usr_conf_nxt(&mut self) -> USR_CONF_NXT_W<USER_SPEC> {
383 USR_CONF_NXT_W::new(self, 15)
384 }
385 #[doc = "Bit 16 - Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state."]
386 #[inline(always)]
387 pub fn sio(&mut self) -> SIO_W<USER_SPEC> {
388 SIO_W::new(self, 16)
389 }
390 #[doc = "Bit 17 - It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state."]
391 #[inline(always)]
392 pub fn usr_hold_pol(&mut self) -> USR_HOLD_POL_W<USER_SPEC> {
393 USR_HOLD_POL_W::new(self, 17)
394 }
395 #[doc = "Bit 18 - spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
396 #[inline(always)]
397 pub fn usr_dout_hold(&mut self) -> USR_DOUT_HOLD_W<USER_SPEC> {
398 USR_DOUT_HOLD_W::new(self, 18)
399 }
400 #[doc = "Bit 19 - spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
401 #[inline(always)]
402 pub fn usr_din_hold(&mut self) -> USR_DIN_HOLD_W<USER_SPEC> {
403 USR_DIN_HOLD_W::new(self, 19)
404 }
405 #[doc = "Bit 20 - spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
406 #[inline(always)]
407 pub fn usr_dummy_hold(&mut self) -> USR_DUMMY_HOLD_W<USER_SPEC> {
408 USR_DUMMY_HOLD_W::new(self, 20)
409 }
410 #[doc = "Bit 21 - spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
411 #[inline(always)]
412 pub fn usr_addr_hold(&mut self) -> USR_ADDR_HOLD_W<USER_SPEC> {
413 USR_ADDR_HOLD_W::new(self, 21)
414 }
415 #[doc = "Bit 22 - spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
416 #[inline(always)]
417 pub fn usr_cmd_hold(&mut self) -> USR_CMD_HOLD_W<USER_SPEC> {
418 USR_CMD_HOLD_W::new(self, 22)
419 }
420 #[doc = "Bit 23 - spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state."]
421 #[inline(always)]
422 pub fn usr_prep_hold(&mut self) -> USR_PREP_HOLD_W<USER_SPEC> {
423 USR_PREP_HOLD_W::new(self, 23)
424 }
425 #[doc = "Bit 24 - read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state."]
426 #[inline(always)]
427 pub fn usr_miso_highpart(&mut self) -> USR_MISO_HIGHPART_W<USER_SPEC> {
428 USR_MISO_HIGHPART_W::new(self, 24)
429 }
430 #[doc = "Bit 25 - write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state."]
431 #[inline(always)]
432 pub fn usr_mosi_highpart(&mut self) -> USR_MOSI_HIGHPART_W<USER_SPEC> {
433 USR_MOSI_HIGHPART_W::new(self, 25)
434 }
435 #[doc = "Bit 26 - spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state."]
436 #[inline(always)]
437 pub fn usr_dummy_idle(&mut self) -> USR_DUMMY_IDLE_W<USER_SPEC> {
438 USR_DUMMY_IDLE_W::new(self, 26)
439 }
440 #[doc = "Bit 27 - This bit enable the write-data phase of an operation. Can be configured in CONF state."]
441 #[inline(always)]
442 pub fn usr_mosi(&mut self) -> USR_MOSI_W<USER_SPEC> {
443 USR_MOSI_W::new(self, 27)
444 }
445 #[doc = "Bit 28 - This bit enable the read-data phase of an operation. Can be configured in CONF state."]
446 #[inline(always)]
447 pub fn usr_miso(&mut self) -> USR_MISO_W<USER_SPEC> {
448 USR_MISO_W::new(self, 28)
449 }
450 #[doc = "Bit 29 - This bit enable the dummy phase of an operation. Can be configured in CONF state."]
451 #[inline(always)]
452 pub fn usr_dummy(&mut self) -> USR_DUMMY_W<USER_SPEC> {
453 USR_DUMMY_W::new(self, 29)
454 }
455 #[doc = "Bit 30 - This bit enable the address phase of an operation. Can be configured in CONF state."]
456 #[inline(always)]
457 pub fn usr_addr(&mut self) -> USR_ADDR_W<USER_SPEC> {
458 USR_ADDR_W::new(self, 30)
459 }
460 #[doc = "Bit 31 - This bit enable the command phase of an operation. Can be configured in CONF state."]
461 #[inline(always)]
462 pub fn usr_command(&mut self) -> USR_COMMAND_W<USER_SPEC> {
463 USR_COMMAND_W::new(self, 31)
464 }
465}
466#[doc = "SPI USER control register\n\nYou can [`read`](crate::Reg::read) this register and get [`user::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`user::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
467pub struct USER_SPEC;
468impl crate::RegisterSpec for USER_SPEC {
469 type Ux = u32;
470}
471#[doc = "`read()` method returns [`user::R`](R) reader structure"]
472impl crate::Readable for USER_SPEC {}
473#[doc = "`write(|w| ..)` method takes [`user::W`](W) writer structure"]
474impl crate::Writable for USER_SPEC {
475 type Safety = crate::Unsafe;
476 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
477 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
478}
479#[doc = "`reset()` method sets USER to value 0x8000_00c0"]
480impl crate::Resettable for USER_SPEC {
481 const RESET_VALUE: u32 = 0x8000_00c0;
482}