esp32s2/interrupt_core0/
clock_gate.rs

1#[doc = "Register `CLOCK_GATE` reader"]
2pub type R = crate::R<CLOCK_GATE_SPEC>;
3#[doc = "Register `CLOCK_GATE` writer"]
4pub type W = crate::W<CLOCK_GATE_SPEC>;
5#[doc = "Field `CLK_EN` reader - This bit is used to enable or disable the clock of interrupt matrix. 1: enable the clock. 0: disable the clock."]
6pub type CLK_EN_R = crate::BitReader;
7#[doc = "Field `CLK_EN` writer - This bit is used to enable or disable the clock of interrupt matrix. 1: enable the clock. 0: disable the clock."]
8pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PRO_NMI_MASK_HW` reader - This bit is used to disable all NMI interrupt signals to CPU."]
10pub type PRO_NMI_MASK_HW_R = crate::BitReader;
11#[doc = "Field `PRO_NMI_MASK_HW` writer - This bit is used to disable all NMI interrupt signals to CPU."]
12pub type PRO_NMI_MASK_HW_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 0 - This bit is used to enable or disable the clock of interrupt matrix. 1: enable the clock. 0: disable the clock."]
15    #[inline(always)]
16    pub fn clk_en(&self) -> CLK_EN_R {
17        CLK_EN_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bit 1 - This bit is used to disable all NMI interrupt signals to CPU."]
20    #[inline(always)]
21    pub fn pro_nmi_mask_hw(&self) -> PRO_NMI_MASK_HW_R {
22        PRO_NMI_MASK_HW_R::new(((self.bits >> 1) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CLOCK_GATE")
29            .field("clk_en", &self.clk_en())
30            .field("pro_nmi_mask_hw", &self.pro_nmi_mask_hw())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bit 0 - This bit is used to enable or disable the clock of interrupt matrix. 1: enable the clock. 0: disable the clock."]
36    #[inline(always)]
37    pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
38        CLK_EN_W::new(self, 0)
39    }
40    #[doc = "Bit 1 - This bit is used to disable all NMI interrupt signals to CPU."]
41    #[inline(always)]
42    pub fn pro_nmi_mask_hw(&mut self) -> PRO_NMI_MASK_HW_W<CLOCK_GATE_SPEC> {
43        PRO_NMI_MASK_HW_W::new(self, 1)
44    }
45}
46#[doc = "NMI interrupt signals mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct CLOCK_GATE_SPEC;
48impl crate::RegisterSpec for CLOCK_GATE_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"]
52impl crate::Readable for CLOCK_GATE_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"]
54impl crate::Writable for CLOCK_GATE_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"]
60impl crate::Resettable for CLOCK_GATE_SPEC {
61    const RESET_VALUE: u32 = 0x01;
62}
esp32s2/interrupt_core0/clock_gate.rs

esp32s2/interrupt_core0/
clock_gate.rs
