Module system

Source
Expand description

System Configuration Registers

Modules§

bt_lpck_div_frac
Divider fraction configuration register for low-power clock
bustoextmem_ena
EDMA enable register
cache_control
Cache control register
clock_gate
Clock gate control register
cpu_intr_from_cpu_0
CPU interrupt controlling register 0
cpu_intr_from_cpu_1
CPU interrupt controlling register 1
cpu_intr_from_cpu_2
CPU interrupt controlling register 2
cpu_intr_from_cpu_3
CPU interrupt controlling register 3
cpu_per_conf
CPU peripheral clock configuration register
cpu_peri_clk_en
CPU peripheral clock enable register
cpu_peri_rst_en
CPU peripheral reset register
date
Version control register
external_device_encrypt_decrypt_control
External memory encrypt and decrypt controlling register
jtag_ctrl_0
JTAG configuration register 0
jtag_ctrl_1
JTAG configuration register 1
jtag_ctrl_2
JTAG configuration register 2
jtag_ctrl_3
JTAG configuration register 3
jtag_ctrl_4
JTAG configuration register 4
jtag_ctrl_5
JTAG configuration register 5
jtag_ctrl_6
JTAG configuration register 6
jtag_ctrl_7
JTAG configuration register 7
lpck_div_int
Low power clock divider integer register
mem_pd_mask
Memory power-related controlling register (under low-sleep)
perip_clk_en0
System peripheral clock (for hardware accelerators) enable register
perip_clk_en1
System peripheral clock (for hardware accelerators) enable register 1
perip_rst_en0
System peripheral (hardware accelerators) reset register 0
perip_rst_en1
System peripheral (hardware accelerators) reset register 1
redundant_eco_ctrl
Redundant ECO control register
rom_ctrl_0
System ROM configuration register 0
rom_ctrl_1
System ROM configuration register 1
rsa_pd_ctrl
RSA memory remapping register
rtc_fastmem_config
RTC fast memory configuration register
rtc_fastmem_crc
RTC fast memory CRC controlling register
sram_ctrl_0
System SRAM configuration register 0
sram_ctrl_1
System SRAM configuration register 1
sram_ctrl_2
System SRAM configuration register 2
sysclk_conf
SoC clock configuration register

Structs§

RegisterBlock
Register block

Type Aliases§

BT_LPCK_DIV_FRAC
BT_LPCK_DIV_FRAC (rw) register accessor: Divider fraction configuration register for low-power clock
BUSTOEXTMEM_ENA
BUSTOEXTMEM_ENA (rw) register accessor: EDMA enable register
CACHE_CONTROL
CACHE_CONTROL (rw) register accessor: Cache control register
CLOCK_GATE
CLOCK_GATE (rw) register accessor: Clock gate control register
CPU_INTR_FROM_CPU_0
CPU_INTR_FROM_CPU_0 (rw) register accessor: CPU interrupt controlling register 0
CPU_INTR_FROM_CPU_1
CPU_INTR_FROM_CPU_1 (rw) register accessor: CPU interrupt controlling register 1
CPU_INTR_FROM_CPU_2
CPU_INTR_FROM_CPU_2 (rw) register accessor: CPU interrupt controlling register 2
CPU_INTR_FROM_CPU_3
CPU_INTR_FROM_CPU_3 (rw) register accessor: CPU interrupt controlling register 3
CPU_PERI_CLK_EN
CPU_PERI_CLK_EN (rw) register accessor: CPU peripheral clock enable register
CPU_PERI_RST_EN
CPU_PERI_RST_EN (rw) register accessor: CPU peripheral reset register
CPU_PER_CONF
CPU_PER_CONF (rw) register accessor: CPU peripheral clock configuration register
DATE
DATE (rw) register accessor: Version control register
EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL
EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL (rw) register accessor: External memory encrypt and decrypt controlling register
JTAG_CTRL_0
JTAG_CTRL_0 (w) register accessor: JTAG configuration register 0
JTAG_CTRL_1
JTAG_CTRL_1 (w) register accessor: JTAG configuration register 1
JTAG_CTRL_2
JTAG_CTRL_2 (w) register accessor: JTAG configuration register 2
JTAG_CTRL_3
JTAG_CTRL_3 (w) register accessor: JTAG configuration register 3
JTAG_CTRL_4
JTAG_CTRL_4 (w) register accessor: JTAG configuration register 4
JTAG_CTRL_5
JTAG_CTRL_5 (w) register accessor: JTAG configuration register 5
JTAG_CTRL_6
JTAG_CTRL_6 (w) register accessor: JTAG configuration register 6
JTAG_CTRL_7
JTAG_CTRL_7 (w) register accessor: JTAG configuration register 7
LPCK_DIV_INT
LPCK_DIV_INT (rw) register accessor: Low power clock divider integer register
MEM_PD_MASK
MEM_PD_MASK (rw) register accessor: Memory power-related controlling register (under low-sleep)
PERIP_CLK_EN0
PERIP_CLK_EN0 (rw) register accessor: System peripheral clock (for hardware accelerators) enable register
PERIP_CLK_EN1
PERIP_CLK_EN1 (rw) register accessor: System peripheral clock (for hardware accelerators) enable register 1
PERIP_RST_EN0
PERIP_RST_EN0 (rw) register accessor: System peripheral (hardware accelerators) reset register 0
PERIP_RST_EN1
PERIP_RST_EN1 (rw) register accessor: System peripheral (hardware accelerators) reset register 1
REDUNDANT_ECO_CTRL
Redundant_ECO_Ctrl (rw) register accessor: Redundant ECO control register
ROM_CTRL_0
ROM_CTRL_0 (rw) register accessor: System ROM configuration register 0
ROM_CTRL_1
ROM_CTRL_1 (rw) register accessor: System ROM configuration register 1
RSA_PD_CTRL
RSA_PD_CTRL (rw) register accessor: RSA memory remapping register
RTC_FASTMEM_CONFIG
RTC_FASTMEM_CONFIG (rw) register accessor: RTC fast memory configuration register
RTC_FASTMEM_CRC
RTC_FASTMEM_CRC (r) register accessor: RTC fast memory CRC controlling register
SRAM_CTRL_0
SRAM_CTRL_0 (rw) register accessor: System SRAM configuration register 0
SRAM_CTRL_1
SRAM_CTRL_1 (rw) register accessor: System SRAM configuration register 1
SRAM_CTRL_2
SRAM_CTRL_2 (rw) register accessor: System SRAM configuration register 2
SYSCLK_CONF
SYSCLK_CONF (rw) register accessor: SoC clock configuration register