esp32s2/
lib.rs

1#![doc = "Peripheral access API for ESP32-S2 microcontrollers (generated using svd2rust v0.37.1 (f74f0b3 2026-04-17))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
2#![allow(non_camel_case_types)]
3#![allow(non_snake_case)]
4#![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
5#![no_std]
6#![cfg_attr(docsrs, feature(doc_cfg))]
7#[doc = r"Number available in the NVIC for configuring priority"]
8pub const NVIC_PRIO_BITS: u8 = 0;
9#[allow(unused_imports)]
10use generic::*;
11#[doc = r"Common register and bit access and modify traits"]
12pub mod generic;
13#[cfg(feature = "rt")]
14extern "C" {
15    fn WIFI_MAC();
16    fn WIFI_NMI();
17    fn WIFI_PWR();
18    fn WIFI_BB();
19    fn BT_MAC();
20    fn BT_BB();
21    fn BT_BB_NMI();
22    fn RWBT();
23    fn RWBLE();
24    fn RWBT_NMI();
25    fn RWBLE_NMI();
26    fn SLC0();
27    fn SLC1();
28    fn UHCI0();
29    fn UHCI1();
30    fn TG0_T0_LEVEL();
31    fn TG0_T1_LEVEL();
32    fn TG0_WDT_LEVEL();
33    fn TG0_LACT_LEVEL();
34    fn TG1_T0_LEVEL();
35    fn TG1_T1_LEVEL();
36    fn TG1_WDT_LEVEL();
37    fn TG1_LACT_LEVEL();
38    fn GPIO();
39    fn GPIO_NMI();
40    fn GPIO_INTR_2();
41    fn GPIO_NMI_2();
42    fn DEDICATED_GPIO();
43    fn FROM_CPU_INTR0();
44    fn FROM_CPU_INTR1();
45    fn FROM_CPU_INTR2();
46    fn FROM_CPU_INTR3();
47    fn SPI1();
48    fn SPI2();
49    fn SPI3();
50    fn I2S0();
51    fn I2S1();
52    fn UART0();
53    fn UART1();
54    fn UART2();
55    fn SDIO_HOST();
56    fn LEDC();
57    fn EFUSE();
58    fn TWAI0();
59    fn USB();
60    fn RTC_CORE();
61    fn RMT();
62    fn PCNT();
63    fn I2C_EXT0();
64    fn I2C_EXT1();
65    fn RSA();
66    fn SHA();
67    fn AES();
68    fn SPI2_DMA();
69    fn SPI3_DMA();
70    fn WDT();
71    fn TIMER1();
72    fn TIMER2();
73    fn TG0_T0_EDGE();
74    fn TG0_T1_EDGE();
75    fn TG0_WDT_EDGE();
76    fn TG0_LACT_EDGE();
77    fn TG1_T0_EDGE();
78    fn TG1_T1_EDGE();
79    fn TG1_WDT_EDGE();
80    fn TG1_LACT_EDGE();
81    fn CACHE_IA();
82    fn SYSTIMER_TARGET0();
83    fn SYSTIMER_TARGET1();
84    fn SYSTIMER_TARGET2();
85    fn PMS_PRO_IRAM0_ILG();
86    fn PMS_PRO_DRAM0_ILG();
87    fn PMS_PRO_DPORT_ILG();
88    fn PMS_PRO_AHB_ILG();
89    fn PMS_PRO_CACHE_ILG();
90    fn PMS_DMA_APB_I_ILG();
91    fn PMS_DMA_RX_I_ILG();
92    fn PMS_DMA_TX_I_ILG();
93    fn SPI0_REJECT_CACHE();
94    fn DMA_COPY();
95    fn SPI4_DMA();
96    fn SPI4();
97    fn ICACHE_PRELOAD();
98    fn DCACHE_PRELOAD();
99    fn APB_ADC();
100    fn CRYPTO_DMA();
101    fn CPU_PERI_ERR();
102    fn APB_PERI_ERR();
103    fn DCACHE_SYNC();
104    fn ICACHE_SYNC();
105}
106#[doc(hidden)]
107#[repr(C)]
108pub union Vector {
109    pub _handler: unsafe extern "C" fn(),
110    _reserved: u32,
111}
112#[cfg(feature = "rt")]
113#[doc(hidden)]
114#[link_section = ".rwtext"]
115#[no_mangle]
116pub static __INTERRUPTS: [Vector; 95] = [
117    Vector { _handler: WIFI_MAC },
118    Vector { _handler: WIFI_NMI },
119    Vector { _handler: WIFI_PWR },
120    Vector { _handler: WIFI_BB },
121    Vector { _handler: BT_MAC },
122    Vector { _handler: BT_BB },
123    Vector {
124        _handler: BT_BB_NMI,
125    },
126    Vector { _handler: RWBT },
127    Vector { _handler: RWBLE },
128    Vector { _handler: RWBT_NMI },
129    Vector {
130        _handler: RWBLE_NMI,
131    },
132    Vector { _handler: SLC0 },
133    Vector { _handler: SLC1 },
134    Vector { _handler: UHCI0 },
135    Vector { _handler: UHCI1 },
136    Vector {
137        _handler: TG0_T0_LEVEL,
138    },
139    Vector {
140        _handler: TG0_T1_LEVEL,
141    },
142    Vector {
143        _handler: TG0_WDT_LEVEL,
144    },
145    Vector {
146        _handler: TG0_LACT_LEVEL,
147    },
148    Vector {
149        _handler: TG1_T0_LEVEL,
150    },
151    Vector {
152        _handler: TG1_T1_LEVEL,
153    },
154    Vector {
155        _handler: TG1_WDT_LEVEL,
156    },
157    Vector {
158        _handler: TG1_LACT_LEVEL,
159    },
160    Vector { _handler: GPIO },
161    Vector { _handler: GPIO_NMI },
162    Vector {
163        _handler: GPIO_INTR_2,
164    },
165    Vector {
166        _handler: GPIO_NMI_2,
167    },
168    Vector {
169        _handler: DEDICATED_GPIO,
170    },
171    Vector {
172        _handler: FROM_CPU_INTR0,
173    },
174    Vector {
175        _handler: FROM_CPU_INTR1,
176    },
177    Vector {
178        _handler: FROM_CPU_INTR2,
179    },
180    Vector {
181        _handler: FROM_CPU_INTR3,
182    },
183    Vector { _handler: SPI1 },
184    Vector { _handler: SPI2 },
185    Vector { _handler: SPI3 },
186    Vector { _handler: I2S0 },
187    Vector { _handler: I2S1 },
188    Vector { _handler: UART0 },
189    Vector { _handler: UART1 },
190    Vector { _handler: UART2 },
191    Vector {
192        _handler: SDIO_HOST,
193    },
194    Vector { _reserved: 0 },
195    Vector { _reserved: 0 },
196    Vector { _reserved: 0 },
197    Vector { _reserved: 0 },
198    Vector { _handler: LEDC },
199    Vector { _handler: EFUSE },
200    Vector { _handler: TWAI0 },
201    Vector { _handler: USB },
202    Vector { _handler: RTC_CORE },
203    Vector { _handler: RMT },
204    Vector { _handler: PCNT },
205    Vector { _handler: I2C_EXT0 },
206    Vector { _handler: I2C_EXT1 },
207    Vector { _handler: RSA },
208    Vector { _handler: SHA },
209    Vector { _handler: AES },
210    Vector { _handler: SPI2_DMA },
211    Vector { _handler: SPI3_DMA },
212    Vector { _handler: WDT },
213    Vector { _handler: TIMER1 },
214    Vector { _handler: TIMER2 },
215    Vector {
216        _handler: TG0_T0_EDGE,
217    },
218    Vector {
219        _handler: TG0_T1_EDGE,
220    },
221    Vector {
222        _handler: TG0_WDT_EDGE,
223    },
224    Vector {
225        _handler: TG0_LACT_EDGE,
226    },
227    Vector {
228        _handler: TG1_T0_EDGE,
229    },
230    Vector {
231        _handler: TG1_T1_EDGE,
232    },
233    Vector {
234        _handler: TG1_WDT_EDGE,
235    },
236    Vector {
237        _handler: TG1_LACT_EDGE,
238    },
239    Vector { _handler: CACHE_IA },
240    Vector {
241        _handler: SYSTIMER_TARGET0,
242    },
243    Vector {
244        _handler: SYSTIMER_TARGET1,
245    },
246    Vector {
247        _handler: SYSTIMER_TARGET2,
248    },
249    Vector { _reserved: 0 },
250    Vector {
251        _handler: PMS_PRO_IRAM0_ILG,
252    },
253    Vector {
254        _handler: PMS_PRO_DRAM0_ILG,
255    },
256    Vector {
257        _handler: PMS_PRO_DPORT_ILG,
258    },
259    Vector {
260        _handler: PMS_PRO_AHB_ILG,
261    },
262    Vector {
263        _handler: PMS_PRO_CACHE_ILG,
264    },
265    Vector {
266        _handler: PMS_DMA_APB_I_ILG,
267    },
268    Vector {
269        _handler: PMS_DMA_RX_I_ILG,
270    },
271    Vector {
272        _handler: PMS_DMA_TX_I_ILG,
273    },
274    Vector {
275        _handler: SPI0_REJECT_CACHE,
276    },
277    Vector { _handler: DMA_COPY },
278    Vector { _handler: SPI4_DMA },
279    Vector { _handler: SPI4 },
280    Vector {
281        _handler: ICACHE_PRELOAD,
282    },
283    Vector {
284        _handler: DCACHE_PRELOAD,
285    },
286    Vector { _handler: APB_ADC },
287    Vector {
288        _handler: CRYPTO_DMA,
289    },
290    Vector {
291        _handler: CPU_PERI_ERR,
292    },
293    Vector {
294        _handler: APB_PERI_ERR,
295    },
296    Vector {
297        _handler: DCACHE_SYNC,
298    },
299    Vector {
300        _handler: ICACHE_SYNC,
301    },
302];
303#[doc = r"Enumeration of all the interrupts."]
304#[cfg_attr(feature = "defmt", derive(defmt::Format))]
305#[derive(Copy, Clone, Debug, PartialEq, Eq)]
306#[repr(u16)]
307pub enum Interrupt {
308    #[doc = "0 - WIFI_MAC"]
309    WIFI_MAC          = 0,
310    #[doc = "1 - WIFI_NMI"]
311    WIFI_NMI          = 1,
312    #[doc = "2 - WIFI_PWR"]
313    WIFI_PWR          = 2,
314    #[doc = "3 - WIFI_BB"]
315    WIFI_BB           = 3,
316    #[doc = "4 - BT_MAC"]
317    BT_MAC            = 4,
318    #[doc = "5 - BT_BB"]
319    BT_BB             = 5,
320    #[doc = "6 - BT_BB_NMI"]
321    BT_BB_NMI         = 6,
322    #[doc = "7 - RWBT"]
323    RWBT              = 7,
324    #[doc = "8 - RWBLE"]
325    RWBLE             = 8,
326    #[doc = "9 - RWBT_NMI"]
327    RWBT_NMI          = 9,
328    #[doc = "10 - RWBLE_NMI"]
329    RWBLE_NMI         = 10,
330    #[doc = "11 - SLC0"]
331    SLC0              = 11,
332    #[doc = "12 - SLC1"]
333    SLC1              = 12,
334    #[doc = "13 - UHCI0"]
335    UHCI0             = 13,
336    #[doc = "14 - UHCI1"]
337    UHCI1             = 14,
338    #[doc = "15 - TG0_T0_LEVEL"]
339    TG0_T0_LEVEL      = 15,
340    #[doc = "16 - TG0_T1_LEVEL"]
341    TG0_T1_LEVEL      = 16,
342    #[doc = "17 - TG0_WDT_LEVEL"]
343    TG0_WDT_LEVEL     = 17,
344    #[doc = "18 - TG0_LACT_LEVEL"]
345    TG0_LACT_LEVEL    = 18,
346    #[doc = "19 - TG1_T0_LEVEL"]
347    TG1_T0_LEVEL      = 19,
348    #[doc = "20 - TG1_T1_LEVEL"]
349    TG1_T1_LEVEL      = 20,
350    #[doc = "21 - TG1_WDT_LEVEL"]
351    TG1_WDT_LEVEL     = 21,
352    #[doc = "22 - TG1_LACT_LEVEL"]
353    TG1_LACT_LEVEL    = 22,
354    #[doc = "23 - GPIO"]
355    GPIO              = 23,
356    #[doc = "24 - GPIO_NMI"]
357    GPIO_NMI          = 24,
358    #[doc = "25 - GPIO_INTR_2"]
359    GPIO_INTR_2       = 25,
360    #[doc = "26 - GPIO_NMI_2"]
361    GPIO_NMI_2        = 26,
362    #[doc = "27 - DEDICATED_GPIO"]
363    DEDICATED_GPIO    = 27,
364    #[doc = "28 - FROM_CPU_INTR0"]
365    FROM_CPU_INTR0    = 28,
366    #[doc = "29 - FROM_CPU_INTR1"]
367    FROM_CPU_INTR1    = 29,
368    #[doc = "30 - FROM_CPU_INTR2"]
369    FROM_CPU_INTR2    = 30,
370    #[doc = "31 - FROM_CPU_INTR3"]
371    FROM_CPU_INTR3    = 31,
372    #[doc = "32 - SPI1"]
373    SPI1              = 32,
374    #[doc = "33 - SPI2"]
375    SPI2              = 33,
376    #[doc = "34 - SPI3"]
377    SPI3              = 34,
378    #[doc = "35 - I2S0"]
379    I2S0              = 35,
380    #[doc = "36 - I2S1"]
381    I2S1              = 36,
382    #[doc = "37 - UART0"]
383    UART0             = 37,
384    #[doc = "38 - UART1"]
385    UART1             = 38,
386    #[doc = "39 - UART2"]
387    UART2             = 39,
388    #[doc = "40 - SDIO_HOST"]
389    SDIO_HOST         = 40,
390    #[doc = "45 - LEDC"]
391    LEDC              = 45,
392    #[doc = "46 - EFUSE"]
393    EFUSE             = 46,
394    #[doc = "47 - TWAI0"]
395    TWAI0             = 47,
396    #[doc = "48 - USB"]
397    USB               = 48,
398    #[doc = "49 - RTC_CORE"]
399    RTC_CORE          = 49,
400    #[doc = "50 - RMT"]
401    RMT               = 50,
402    #[doc = "51 - PCNT"]
403    PCNT              = 51,
404    #[doc = "52 - I2C_EXT0"]
405    I2C_EXT0          = 52,
406    #[doc = "53 - I2C_EXT1"]
407    I2C_EXT1          = 53,
408    #[doc = "54 - RSA"]
409    RSA               = 54,
410    #[doc = "55 - SHA"]
411    SHA               = 55,
412    #[doc = "56 - AES"]
413    AES               = 56,
414    #[doc = "57 - SPI2_DMA"]
415    SPI2_DMA          = 57,
416    #[doc = "58 - SPI3_DMA"]
417    SPI3_DMA          = 58,
418    #[doc = "59 - WDT"]
419    WDT               = 59,
420    #[doc = "60 - TIMER1"]
421    TIMER1            = 60,
422    #[doc = "61 - TIMER2"]
423    TIMER2            = 61,
424    #[doc = "62 - TG0_T0_EDGE"]
425    TG0_T0_EDGE       = 62,
426    #[doc = "63 - TG0_T1_EDGE"]
427    TG0_T1_EDGE       = 63,
428    #[doc = "64 - TG0_WDT_EDGE"]
429    TG0_WDT_EDGE      = 64,
430    #[doc = "65 - TG0_LACT_EDGE"]
431    TG0_LACT_EDGE     = 65,
432    #[doc = "66 - TG1_T0_EDGE"]
433    TG1_T0_EDGE       = 66,
434    #[doc = "67 - TG1_T1_EDGE"]
435    TG1_T1_EDGE       = 67,
436    #[doc = "68 - TG1_WDT_EDGE"]
437    TG1_WDT_EDGE      = 68,
438    #[doc = "69 - TG1_LACT_EDGE"]
439    TG1_LACT_EDGE     = 69,
440    #[doc = "70 - CACHE_IA"]
441    CACHE_IA          = 70,
442    #[doc = "71 - SYSTIMER_TARGET0"]
443    SYSTIMER_TARGET0  = 71,
444    #[doc = "72 - SYSTIMER_TARGET1"]
445    SYSTIMER_TARGET1  = 72,
446    #[doc = "73 - SYSTIMER_TARGET2"]
447    SYSTIMER_TARGET2  = 73,
448    #[doc = "75 - PMS_PRO_IRAM0_ILG"]
449    PMS_PRO_IRAM0_ILG = 75,
450    #[doc = "76 - PMS_PRO_DRAM0_ILG"]
451    PMS_PRO_DRAM0_ILG = 76,
452    #[doc = "77 - PMS_PRO_DPORT_ILG"]
453    PMS_PRO_DPORT_ILG = 77,
454    #[doc = "78 - PMS_PRO_AHB_ILG"]
455    PMS_PRO_AHB_ILG   = 78,
456    #[doc = "79 - PMS_PRO_CACHE_ILG"]
457    PMS_PRO_CACHE_ILG = 79,
458    #[doc = "80 - PMS_DMA_APB_I_ILG"]
459    PMS_DMA_APB_I_ILG = 80,
460    #[doc = "81 - PMS_DMA_RX_I_ILG"]
461    PMS_DMA_RX_I_ILG  = 81,
462    #[doc = "82 - PMS_DMA_TX_I_ILG"]
463    PMS_DMA_TX_I_ILG  = 82,
464    #[doc = "83 - SPI0_REJECT_CACHE"]
465    SPI0_REJECT_CACHE = 83,
466    #[doc = "84 - DMA_COPY"]
467    DMA_COPY          = 84,
468    #[doc = "85 - SPI4_DMA"]
469    SPI4_DMA          = 85,
470    #[doc = "86 - SPI4"]
471    SPI4              = 86,
472    #[doc = "87 - ICACHE_PRELOAD"]
473    ICACHE_PRELOAD    = 87,
474    #[doc = "88 - DCACHE_PRELOAD"]
475    DCACHE_PRELOAD    = 88,
476    #[doc = "89 - APB_ADC"]
477    APB_ADC           = 89,
478    #[doc = "90 - CRYPTO_DMA"]
479    CRYPTO_DMA        = 90,
480    #[doc = "91 - CPU_PERI_ERR"]
481    CPU_PERI_ERR      = 91,
482    #[doc = "92 - APB_PERI_ERR"]
483    APB_PERI_ERR      = 92,
484    #[doc = "93 - DCACHE_SYNC"]
485    DCACHE_SYNC       = 93,
486    #[doc = "94 - ICACHE_SYNC"]
487    ICACHE_SYNC       = 94,
488}
489#[doc = r" TryFromInterruptError"]
490#[cfg_attr(feature = "defmt", derive(defmt::Format))]
491#[derive(Debug, Copy, Clone)]
492pub struct TryFromInterruptError(());
493impl Interrupt {
494    #[doc = r" Attempt to convert a given value into an `Interrupt`"]
495    #[inline]
496    pub fn try_from(value: u16) -> Result<Self, TryFromInterruptError> {
497        match value {
498            0 => Ok(Interrupt::WIFI_MAC),
499            1 => Ok(Interrupt::WIFI_NMI),
500            2 => Ok(Interrupt::WIFI_PWR),
501            3 => Ok(Interrupt::WIFI_BB),
502            4 => Ok(Interrupt::BT_MAC),
503            5 => Ok(Interrupt::BT_BB),
504            6 => Ok(Interrupt::BT_BB_NMI),
505            7 => Ok(Interrupt::RWBT),
506            8 => Ok(Interrupt::RWBLE),
507            9 => Ok(Interrupt::RWBT_NMI),
508            10 => Ok(Interrupt::RWBLE_NMI),
509            11 => Ok(Interrupt::SLC0),
510            12 => Ok(Interrupt::SLC1),
511            13 => Ok(Interrupt::UHCI0),
512            14 => Ok(Interrupt::UHCI1),
513            15 => Ok(Interrupt::TG0_T0_LEVEL),
514            16 => Ok(Interrupt::TG0_T1_LEVEL),
515            17 => Ok(Interrupt::TG0_WDT_LEVEL),
516            18 => Ok(Interrupt::TG0_LACT_LEVEL),
517            19 => Ok(Interrupt::TG1_T0_LEVEL),
518            20 => Ok(Interrupt::TG1_T1_LEVEL),
519            21 => Ok(Interrupt::TG1_WDT_LEVEL),
520            22 => Ok(Interrupt::TG1_LACT_LEVEL),
521            23 => Ok(Interrupt::GPIO),
522            24 => Ok(Interrupt::GPIO_NMI),
523            25 => Ok(Interrupt::GPIO_INTR_2),
524            26 => Ok(Interrupt::GPIO_NMI_2),
525            27 => Ok(Interrupt::DEDICATED_GPIO),
526            28 => Ok(Interrupt::FROM_CPU_INTR0),
527            29 => Ok(Interrupt::FROM_CPU_INTR1),
528            30 => Ok(Interrupt::FROM_CPU_INTR2),
529            31 => Ok(Interrupt::FROM_CPU_INTR3),
530            32 => Ok(Interrupt::SPI1),
531            33 => Ok(Interrupt::SPI2),
532            34 => Ok(Interrupt::SPI3),
533            35 => Ok(Interrupt::I2S0),
534            36 => Ok(Interrupt::I2S1),
535            37 => Ok(Interrupt::UART0),
536            38 => Ok(Interrupt::UART1),
537            39 => Ok(Interrupt::UART2),
538            40 => Ok(Interrupt::SDIO_HOST),
539            45 => Ok(Interrupt::LEDC),
540            46 => Ok(Interrupt::EFUSE),
541            47 => Ok(Interrupt::TWAI0),
542            48 => Ok(Interrupt::USB),
543            49 => Ok(Interrupt::RTC_CORE),
544            50 => Ok(Interrupt::RMT),
545            51 => Ok(Interrupt::PCNT),
546            52 => Ok(Interrupt::I2C_EXT0),
547            53 => Ok(Interrupt::I2C_EXT1),
548            54 => Ok(Interrupt::RSA),
549            55 => Ok(Interrupt::SHA),
550            56 => Ok(Interrupt::AES),
551            57 => Ok(Interrupt::SPI2_DMA),
552            58 => Ok(Interrupt::SPI3_DMA),
553            59 => Ok(Interrupt::WDT),
554            60 => Ok(Interrupt::TIMER1),
555            61 => Ok(Interrupt::TIMER2),
556            62 => Ok(Interrupt::TG0_T0_EDGE),
557            63 => Ok(Interrupt::TG0_T1_EDGE),
558            64 => Ok(Interrupt::TG0_WDT_EDGE),
559            65 => Ok(Interrupt::TG0_LACT_EDGE),
560            66 => Ok(Interrupt::TG1_T0_EDGE),
561            67 => Ok(Interrupt::TG1_T1_EDGE),
562            68 => Ok(Interrupt::TG1_WDT_EDGE),
563            69 => Ok(Interrupt::TG1_LACT_EDGE),
564            70 => Ok(Interrupt::CACHE_IA),
565            71 => Ok(Interrupt::SYSTIMER_TARGET0),
566            72 => Ok(Interrupt::SYSTIMER_TARGET1),
567            73 => Ok(Interrupt::SYSTIMER_TARGET2),
568            75 => Ok(Interrupt::PMS_PRO_IRAM0_ILG),
569            76 => Ok(Interrupt::PMS_PRO_DRAM0_ILG),
570            77 => Ok(Interrupt::PMS_PRO_DPORT_ILG),
571            78 => Ok(Interrupt::PMS_PRO_AHB_ILG),
572            79 => Ok(Interrupt::PMS_PRO_CACHE_ILG),
573            80 => Ok(Interrupt::PMS_DMA_APB_I_ILG),
574            81 => Ok(Interrupt::PMS_DMA_RX_I_ILG),
575            82 => Ok(Interrupt::PMS_DMA_TX_I_ILG),
576            83 => Ok(Interrupt::SPI0_REJECT_CACHE),
577            84 => Ok(Interrupt::DMA_COPY),
578            85 => Ok(Interrupt::SPI4_DMA),
579            86 => Ok(Interrupt::SPI4),
580            87 => Ok(Interrupt::ICACHE_PRELOAD),
581            88 => Ok(Interrupt::DCACHE_PRELOAD),
582            89 => Ok(Interrupt::APB_ADC),
583            90 => Ok(Interrupt::CRYPTO_DMA),
584            91 => Ok(Interrupt::CPU_PERI_ERR),
585            92 => Ok(Interrupt::APB_PERI_ERR),
586            93 => Ok(Interrupt::DCACHE_SYNC),
587            94 => Ok(Interrupt::ICACHE_SYNC),
588            _ => Err(TryFromInterruptError(())),
589        }
590    }
591}
592#[doc = "AES (Advanced Encryption Standard) Accelerator"]
593pub type AES = crate::Periph<aes::RegisterBlock, 0x6003_a000>;
594impl core::fmt::Debug for AES {
595    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
596        f.debug_struct("AES").finish()
597    }
598}
599#[doc = "AES (Advanced Encryption Standard) Accelerator"]
600pub mod aes;
601#[doc = "SAR (Successive Approximation Register) Analog-to-Digital Converter"]
602pub type APB_SARADC = crate::Periph<apb_saradc::RegisterBlock, 0x3f44_0000>;
603impl core::fmt::Debug for APB_SARADC {
604    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
605        f.debug_struct("APB_SARADC").finish()
606    }
607}
608#[doc = "SAR (Successive Approximation Register) Analog-to-Digital Converter"]
609pub mod apb_saradc;
610#[doc = "BB Peripheral"]
611pub type BB = crate::Periph<bb::RegisterBlock, 0x3f41_d000>;
612impl core::fmt::Debug for BB {
613    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
614        f.debug_struct("BB").finish()
615    }
616}
617#[doc = "BB Peripheral"]
618pub mod bb;
619#[doc = "DEDICATED_GPIO Peripheral"]
620pub type DEDICATED_GPIO = crate::Periph<dedicated_gpio::RegisterBlock, 0x3f4c_f000>;
621impl core::fmt::Debug for DEDICATED_GPIO {
622    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
623        f.debug_struct("DEDICATED_GPIO").finish()
624    }
625}
626#[doc = "DEDICATED_GPIO Peripheral"]
627pub mod dedicated_gpio;
628#[doc = "I2C Analog Master"]
629pub type I2C_ANA_MST = crate::Periph<i2c_ana_mst::RegisterBlock, 0x6000_e000>;
630impl core::fmt::Debug for I2C_ANA_MST {
631    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
632        f.debug_struct("I2C_ANA_MST").finish()
633    }
634}
635#[doc = "I2C Analog Master"]
636pub mod i2c_ana_mst;
637#[doc = "MAC controller for Wi-Fi peripheral"]
638pub type WIFI = crate::Periph<wifi::RegisterBlock, 0x6003_3000>;
639impl core::fmt::Debug for WIFI {
640    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
641        f.debug_struct("WIFI").finish()
642    }
643}
644#[doc = "MAC controller for Wi-Fi peripheral"]
645pub mod wifi;
646#[doc = "Digital Signature"]
647pub type DS = crate::Periph<ds::RegisterBlock, 0x6003_d000>;
648impl core::fmt::Debug for DS {
649    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
650        f.debug_struct("DS").finish()
651    }
652}
653#[doc = "Digital Signature"]
654pub mod ds;
655#[doc = "eFuse Controller"]
656pub type EFUSE = crate::Periph<efuse::RegisterBlock, 0x3f41_a000>;
657impl core::fmt::Debug for EFUSE {
658    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
659        f.debug_struct("EFUSE").finish()
660    }
661}
662#[doc = "eFuse Controller"]
663pub mod efuse;
664#[doc = "NRX Peripheral"]
665pub type NRX = crate::Periph<nrx::RegisterBlock, 0x3f41_cc00>;
666impl core::fmt::Debug for NRX {
667    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
668        f.debug_struct("NRX").finish()
669    }
670}
671#[doc = "NRX Peripheral"]
672pub mod nrx;
673#[doc = "External Memory"]
674pub type EXTMEM = crate::Periph<extmem::RegisterBlock, 0x6180_0000>;
675impl core::fmt::Debug for EXTMEM {
676    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
677        f.debug_struct("EXTMEM").finish()
678    }
679}
680#[doc = "External Memory"]
681pub mod extmem;
682#[doc = "General Purpose Input/Output"]
683pub type GPIO = crate::Periph<gpio::RegisterBlock, 0x3f40_4000>;
684impl core::fmt::Debug for GPIO {
685    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
686        f.debug_struct("GPIO").finish()
687    }
688}
689#[doc = "General Purpose Input/Output"]
690pub mod gpio;
691#[doc = "Sigma-Delta Modulation"]
692pub type GPIO_SD = crate::Periph<gpio_sd::RegisterBlock, 0x3f40_4f00>;
693impl core::fmt::Debug for GPIO_SD {
694    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
695        f.debug_struct("GPIO_SD").finish()
696    }
697}
698#[doc = "Sigma-Delta Modulation"]
699pub mod gpio_sd;
700#[doc = "FE2 Peripheral"]
701pub type FE2 = crate::Periph<fe2::RegisterBlock, 0x3f40_5000>;
702impl core::fmt::Debug for FE2 {
703    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
704        f.debug_struct("FE2").finish()
705    }
706}
707#[doc = "FE2 Peripheral"]
708pub mod fe2;
709#[doc = "FE Peripheral"]
710pub type FE = crate::Periph<fe::RegisterBlock, 0x3f40_6000>;
711impl core::fmt::Debug for FE {
712    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
713        f.debug_struct("FE").finish()
714    }
715}
716#[doc = "FE Peripheral"]
717pub mod fe;
718#[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"]
719pub type HMAC = crate::Periph<hmac::RegisterBlock, 0x6003_e000>;
720impl core::fmt::Debug for HMAC {
721    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
722        f.debug_struct("HMAC").finish()
723    }
724}
725#[doc = "HMAC (Hash-based Message Authentication Code) Accelerator"]
726pub mod hmac;
727#[doc = "Crypto DMA Controller"]
728pub type CRYPTO_DMA = crate::Periph<crypto_dma::RegisterBlock, 0x6003_f000>;
729impl core::fmt::Debug for CRYPTO_DMA {
730    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
731        f.debug_struct("CRYPTO_DMA").finish()
732    }
733}
734#[doc = "Crypto DMA Controller"]
735pub mod crypto_dma;
736#[doc = "I2C (Inter-Integrated Circuit) Controller 0"]
737pub type I2C0 = crate::Periph<i2c0::RegisterBlock, 0x3f41_3000>;
738impl core::fmt::Debug for I2C0 {
739    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
740        f.debug_struct("I2C0").finish()
741    }
742}
743#[doc = "I2C (Inter-Integrated Circuit) Controller 0"]
744pub mod i2c0;
745#[doc = "I2C (Inter-Integrated Circuit) Controller 1"]
746pub type I2C1 = crate::Periph<i2c0::RegisterBlock, 0x3f42_7000>;
747impl core::fmt::Debug for I2C1 {
748    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
749        f.debug_struct("I2C1").finish()
750    }
751}
752#[doc = "I2C (Inter-Integrated Circuit) Controller 1"]
753pub use self::i2c0 as i2c1;
754#[doc = "I2S (Inter-IC Sound) Controller 0"]
755pub type I2S0 = crate::Periph<i2s0::RegisterBlock, 0x3f40_f000>;
756impl core::fmt::Debug for I2S0 {
757    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
758        f.debug_struct("I2S0").finish()
759    }
760}
761#[doc = "I2S (Inter-IC Sound) Controller 0"]
762pub mod i2s0;
763#[doc = "Interrupt Controller (Core 0)"]
764pub type INTERRUPT_CORE0 = crate::Periph<interrupt_core0::RegisterBlock, 0x3f4c_2000>;
765impl core::fmt::Debug for INTERRUPT_CORE0 {
766    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
767        f.debug_struct("INTERRUPT_CORE0").finish()
768    }
769}
770#[doc = "Interrupt Controller (Core 0)"]
771pub mod interrupt_core0;
772#[doc = "Copy DMA Controller"]
773pub type COPY_DMA = crate::Periph<copy_dma::RegisterBlock, 0x3f4c_3000>;
774impl core::fmt::Debug for COPY_DMA {
775    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
776        f.debug_struct("COPY_DMA").finish()
777    }
778}
779#[doc = "Copy DMA Controller"]
780pub mod copy_dma;
781#[doc = "Input/Output Multiplexer"]
782pub type IO_MUX = crate::Periph<io_mux::RegisterBlock, 0x3f40_9000>;
783impl core::fmt::Debug for IO_MUX {
784    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
785        f.debug_struct("IO_MUX").finish()
786    }
787}
788#[doc = "Input/Output Multiplexer"]
789pub mod io_mux;
790#[doc = "LED Control PWM (Pulse Width Modulation)"]
791pub type LEDC = crate::Periph<ledc::RegisterBlock, 0x3f41_9000>;
792impl core::fmt::Debug for LEDC {
793    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
794        f.debug_struct("LEDC").finish()
795    }
796}
797#[doc = "LED Control PWM (Pulse Width Modulation)"]
798pub mod ledc;
799#[doc = "Pulse Count Controller"]
800pub type PCNT = crate::Periph<pcnt::RegisterBlock, 0x3f41_7000>;
801impl core::fmt::Debug for PCNT {
802    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
803        f.debug_struct("PCNT").finish()
804    }
805}
806#[doc = "Pulse Count Controller"]
807pub mod pcnt;
808#[doc = "Permissions Controller"]
809pub type PMS = crate::Periph<pms::RegisterBlock, 0x3f4c_1000>;
810impl core::fmt::Debug for PMS {
811    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
812        f.debug_struct("PMS").finish()
813    }
814}
815#[doc = "Permissions Controller"]
816pub mod pms;
817#[doc = "Remote Control"]
818pub type RMT = crate::Periph<rmt::RegisterBlock, 0x3f41_6000>;
819impl core::fmt::Debug for RMT {
820    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
821        f.debug_struct("RMT").finish()
822    }
823}
824#[doc = "Remote Control"]
825pub mod rmt;
826#[doc = "Hardware Random Number Generator"]
827pub type RNG = crate::Periph<rng::RegisterBlock, 0x6003_5000>;
828impl core::fmt::Debug for RNG {
829    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
830        f.debug_struct("RNG").finish()
831    }
832}
833#[doc = "Hardware Random Number Generator"]
834pub mod rng;
835#[doc = "RSA (Rivest Shamir Adleman) Accelerator"]
836pub type RSA = crate::Periph<rsa::RegisterBlock, 0x6003_c000>;
837impl core::fmt::Debug for RSA {
838    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
839        f.debug_struct("RSA").finish()
840    }
841}
842#[doc = "RSA (Rivest Shamir Adleman) Accelerator"]
843pub mod rsa;
844#[doc = "Low-power Input/Output"]
845pub type RTC_IO = crate::Periph<rtc_io::RegisterBlock, 0x3f40_8400>;
846impl core::fmt::Debug for RTC_IO {
847    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
848        f.debug_struct("RTC_IO").finish()
849    }
850}
851#[doc = "Low-power Input/Output"]
852pub mod rtc_io;
853#[doc = "Real-Time Clock Control"]
854pub type RTC_CNTL = crate::Periph<rtc_cntl::RegisterBlock, 0x3f40_8000>;
855impl core::fmt::Debug for RTC_CNTL {
856    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
857        f.debug_struct("RTC_CNTL").finish()
858    }
859}
860#[doc = "Real-Time Clock Control"]
861pub mod rtc_cntl;
862#[doc = "Low-power I2C (Inter-Integrated Circuit) Controller"]
863pub type RTC_I2C = crate::Periph<rtc_i2c::RegisterBlock, 0x3f40_8c00>;
864impl core::fmt::Debug for RTC_I2C {
865    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
866        f.debug_struct("RTC_I2C").finish()
867    }
868}
869#[doc = "Low-power I2C (Inter-Integrated Circuit) Controller"]
870pub mod rtc_i2c;
871#[doc = "SENS Peripheral"]
872pub type SENS = crate::Periph<sens::RegisterBlock, 0x3f40_8800>;
873impl core::fmt::Debug for SENS {
874    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
875        f.debug_struct("SENS").finish()
876    }
877}
878#[doc = "SENS Peripheral"]
879pub mod sens;
880#[doc = "SHA (Secure Hash Algorithm) Accelerator"]
881pub type SHA = crate::Periph<sha::RegisterBlock, 0x6003_b000>;
882impl core::fmt::Debug for SHA {
883    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
884        f.debug_struct("SHA").finish()
885    }
886}
887#[doc = "SHA (Secure Hash Algorithm) Accelerator"]
888pub mod sha;
889#[doc = "SPI (Serial Peripheral Interface) Controller 2 (GPSPI)"]
890pub type SPI2 = crate::Periph<spi2::RegisterBlock, 0x3f42_4000>;
891impl core::fmt::Debug for SPI2 {
892    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
893        f.debug_struct("SPI2").finish()
894    }
895}
896#[doc = "SPI (Serial Peripheral Interface) Controller 2 (GPSPI)"]
897pub mod spi2;
898#[doc = "SPI (Serial Peripheral Interface) Controller 1"]
899pub type SPI1 = crate::Periph<spi0::RegisterBlock, 0x3f40_2000>;
900impl core::fmt::Debug for SPI1 {
901    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
902        f.debug_struct("SPI1").finish()
903    }
904}
905#[doc = "SPI (Serial Peripheral Interface) Controller 1"]
906pub use self::spi0 as spi1;
907#[doc = "SPI (Serial Peripheral Interface) Controller 0 (MEMSPI)"]
908pub type SPI0 = crate::Periph<spi0::RegisterBlock, 0x3f40_3000>;
909impl core::fmt::Debug for SPI0 {
910    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
911        f.debug_struct("SPI0").finish()
912    }
913}
914#[doc = "SPI (Serial Peripheral Interface) Controller 0 (MEMSPI)"]
915pub mod spi0;
916#[doc = "SPI (Serial Peripheral Interface) Controller 3"]
917pub type SPI3 = crate::Periph<spi2::RegisterBlock, 0x3f42_5000>;
918impl core::fmt::Debug for SPI3 {
919    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
920        f.debug_struct("SPI3").finish()
921    }
922}
923#[doc = "SPI (Serial Peripheral Interface) Controller 3"]
924pub use self::spi2 as spi3;
925#[doc = "SPI (Serial Peripheral Interface) Controller 4"]
926pub type SPI4 = crate::Periph<spi2::RegisterBlock, 0x3f43_7000>;
927impl core::fmt::Debug for SPI4 {
928    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
929        f.debug_struct("SPI4").finish()
930    }
931}
932#[doc = "SPI (Serial Peripheral Interface) Controller 4"]
933pub use self::spi2 as spi4;
934#[doc = "SYSCON Peripheral"]
935pub type SYSCON = crate::Periph<syscon::RegisterBlock, 0x3f42_6000>;
936impl core::fmt::Debug for SYSCON {
937    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
938        f.debug_struct("SYSCON").finish()
939    }
940}
941#[doc = "SYSCON Peripheral"]
942pub mod syscon;
943#[doc = "System Configuration Registers"]
944pub type SYSTEM = crate::Periph<system::RegisterBlock, 0x3f4c_0000>;
945impl core::fmt::Debug for SYSTEM {
946    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
947        f.debug_struct("SYSTEM").finish()
948    }
949}
950#[doc = "System Configuration Registers"]
951pub mod system;
952#[doc = "System Timer"]
953pub type SYSTIMER = crate::Periph<systimer::RegisterBlock, 0x3f42_3000>;
954impl core::fmt::Debug for SYSTIMER {
955    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
956        f.debug_struct("SYSTIMER").finish()
957    }
958}
959#[doc = "System Timer"]
960pub mod systimer;
961#[doc = "Timer Group 0"]
962pub type TIMG0 = crate::Periph<timg0::RegisterBlock, 0x3f41_f000>;
963impl core::fmt::Debug for TIMG0 {
964    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
965        f.debug_struct("TIMG0").finish()
966    }
967}
968#[doc = "Timer Group 0"]
969pub mod timg0;
970#[doc = "Timer Group 1"]
971pub type TIMG1 = crate::Periph<timg0::RegisterBlock, 0x3f42_0000>;
972impl core::fmt::Debug for TIMG1 {
973    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
974        f.debug_struct("TIMG1").finish()
975    }
976}
977#[doc = "Timer Group 1"]
978pub use self::timg0 as timg1;
979#[doc = "Two-Wire Automotive Interface"]
980pub type TWAI0 = crate::Periph<twai0::RegisterBlock, 0x3f42_b000>;
981impl core::fmt::Debug for TWAI0 {
982    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
983        f.debug_struct("TWAI0").finish()
984    }
985}
986#[doc = "Two-Wire Automotive Interface"]
987pub mod twai0;
988#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"]
989pub type UART0 = crate::Periph<uart0::RegisterBlock, 0x3f40_0000>;
990impl core::fmt::Debug for UART0 {
991    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
992        f.debug_struct("UART0").finish()
993    }
994}
995#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 0"]
996pub mod uart0;
997#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"]
998pub type UART1 = crate::Periph<uart0::RegisterBlock, 0x3f41_0000>;
999impl core::fmt::Debug for UART1 {
1000    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1001        f.debug_struct("UART1").finish()
1002    }
1003}
1004#[doc = "UART (Universal Asynchronous Receiver-Transmitter) Controller 1"]
1005pub use self::uart0 as uart1;
1006#[doc = "Universal Host Controller Interface 0"]
1007pub type UHCI0 = crate::Periph<uhci0::RegisterBlock, 0x3f41_4000>;
1008impl core::fmt::Debug for UHCI0 {
1009    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1010        f.debug_struct("UHCI0").finish()
1011    }
1012}
1013#[doc = "Universal Host Controller Interface 0"]
1014pub mod uhci0;
1015#[doc = "USB OTG (On-The-Go)"]
1016pub type USB0 = crate::Periph<usb0::RegisterBlock, 0x6008_0000>;
1017impl core::fmt::Debug for USB0 {
1018    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1019        f.debug_struct("USB0").finish()
1020    }
1021}
1022#[doc = "USB OTG (On-The-Go)"]
1023pub mod usb0;
1024#[doc = "USB_WRAP Peripheral"]
1025pub type USB_WRAP = crate::Periph<usb_wrap::RegisterBlock, 0x3f43_9000>;
1026impl core::fmt::Debug for USB_WRAP {
1027    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1028        f.debug_struct("USB_WRAP").finish()
1029    }
1030}
1031#[doc = "USB_WRAP Peripheral"]
1032pub mod usb_wrap;
1033#[doc = "XTS-AES-128 Flash Encryption"]
1034pub type XTS_AES = crate::Periph<xts_aes::RegisterBlock, 0x6003_a100>;
1035impl core::fmt::Debug for XTS_AES {
1036    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1037        f.debug_struct("XTS_AES").finish()
1038    }
1039}
1040#[doc = "XTS-AES-128 Flash Encryption"]
1041pub mod xts_aes;
esp32s2/lib.rs

esp32s2/
lib.rs
