esp32s2 0.31.2

Peripheral access crate for the ESP32-S2
Documentation 
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#[doc = "Register `PRO_CACHE_ACS_CNT_CLR` writer"]
pub type W = crate::W<PRO_CACHE_ACS_CNT_CLR_SPEC>;
#[doc = "Field `PRO_DCACHE_ACS_CNT_CLR` writer - The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG, DC_PRELOAD_EVICT_CNT_REG, DC_PRELOAD_MISS_CNT_REG, DBUS0-2_ABANDON_CNT_REG, DBUS0-2_ACS_WB_CNT_REG, DBUS0-2_ACS_MISS_CNT_REG and DBUS0-2_ACS_CNT_REG."]
pub type PRO_DCACHE_ACS_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PRO_ICACHE_ACS_CNT_CLR` writer - The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG, IC_PRELOAD_MISS_CNT_REG, IBUS0-2_ABANDON_CNT_REG, IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG."]
pub type PRO_ICACHE_ACS_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_ACS_CNT_CLR_SPEC> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        write!(f, "(not readable)")
    }
}
impl W {
    #[doc = "Bit 0 - The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG, DC_PRELOAD_EVICT_CNT_REG, DC_PRELOAD_MISS_CNT_REG, DBUS0-2_ABANDON_CNT_REG, DBUS0-2_ACS_WB_CNT_REG, DBUS0-2_ACS_MISS_CNT_REG and DBUS0-2_ACS_CNT_REG."]
    #[inline(always)]
    pub fn pro_dcache_acs_cnt_clr(
        &mut self,
    ) -> PRO_DCACHE_ACS_CNT_CLR_W<'_, PRO_CACHE_ACS_CNT_CLR_SPEC> {
        PRO_DCACHE_ACS_CNT_CLR_W::new(self, 0)
    }
    #[doc = "Bit 1 - The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG, IC_PRELOAD_MISS_CNT_REG, IBUS0-2_ABANDON_CNT_REG, IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG."]
    #[inline(always)]
    pub fn pro_icache_acs_cnt_clr(
        &mut self,
    ) -> PRO_ICACHE_ACS_CNT_CLR_W<'_, PRO_CACHE_ACS_CNT_CLR_SPEC> {
        PRO_ICACHE_ACS_CNT_CLR_W::new(self, 1)
    }
}
#[doc = "register description\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_cache_acs_cnt_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PRO_CACHE_ACS_CNT_CLR_SPEC;
impl crate::RegisterSpec for PRO_CACHE_ACS_CNT_CLR_SPEC {
    type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`pro_cache_acs_cnt_clr::W`](W) writer structure"]
impl crate::Writable for PRO_CACHE_ACS_CNT_CLR_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PRO_CACHE_ACS_CNT_CLR to value 0"]
impl crate::Resettable for PRO_CACHE_ACS_CNT_CLR_SPEC {}