esp32s2 0.31.1

Peripheral access crate for the ESP32-S2
Documentation 
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#[doc = "Register `PRO_DRAM0_2` reader"]
pub type R = crate::R<PRO_DRAM0_2_SPEC>;
#[doc = "Register `PRO_DRAM0_2` writer"]
pub type W = crate::W<PRO_DRAM0_2_SPEC>;
#[doc = "Field `PRO_DRAM0_RTCFAST_SPLTADDR` reader - Configure the split address of RTC FAST for DBUS0 access."]
pub type PRO_DRAM0_RTCFAST_SPLTADDR_R = crate::FieldReader<u16>;
#[doc = "Field `PRO_DRAM0_RTCFAST_SPLTADDR` writer - Configure the split address of RTC FAST for DBUS0 access."]
pub type PRO_DRAM0_RTCFAST_SPLTADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
#[doc = "Field `PRO_DRAM0_RTCFAST_L_R` reader - Setting to 1 grants DBUS0 permission to read RTC FAST low address region."]
pub type PRO_DRAM0_RTCFAST_L_R_R = crate::BitReader;
#[doc = "Field `PRO_DRAM0_RTCFAST_L_R` writer - Setting to 1 grants DBUS0 permission to read RTC FAST low address region."]
pub type PRO_DRAM0_RTCFAST_L_R_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PRO_DRAM0_RTCFAST_L_W` reader - Setting to 1 grants DBUS0 permission to write RTC FAST low address region."]
pub type PRO_DRAM0_RTCFAST_L_W_R = crate::BitReader;
#[doc = "Field `PRO_DRAM0_RTCFAST_L_W` writer - Setting to 1 grants DBUS0 permission to write RTC FAST low address region."]
pub type PRO_DRAM0_RTCFAST_L_W_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PRO_DRAM0_RTCFAST_H_R` reader - Setting to 1 grants DBUS0 permission to read RTC FAST high address region."]
pub type PRO_DRAM0_RTCFAST_H_R_R = crate::BitReader;
#[doc = "Field `PRO_DRAM0_RTCFAST_H_R` writer - Setting to 1 grants DBUS0 permission to read RTC FAST high address region."]
pub type PRO_DRAM0_RTCFAST_H_R_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PRO_DRAM0_RTCFAST_H_W` reader - Setting to 1 grants DBUS0 permission to write RTC FAST high address region."]
pub type PRO_DRAM0_RTCFAST_H_W_R = crate::BitReader;
#[doc = "Field `PRO_DRAM0_RTCFAST_H_W` writer - Setting to 1 grants DBUS0 permission to write RTC FAST high address region."]
pub type PRO_DRAM0_RTCFAST_H_W_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bits 0:10 - Configure the split address of RTC FAST for DBUS0 access."]
    #[inline(always)]
    pub fn pro_dram0_rtcfast_spltaddr(&self) -> PRO_DRAM0_RTCFAST_SPLTADDR_R {
        PRO_DRAM0_RTCFAST_SPLTADDR_R::new((self.bits & 0x07ff) as u16)
    }
    #[doc = "Bit 11 - Setting to 1 grants DBUS0 permission to read RTC FAST low address region."]
    #[inline(always)]
    pub fn pro_dram0_rtcfast_l_r(&self) -> PRO_DRAM0_RTCFAST_L_R_R {
        PRO_DRAM0_RTCFAST_L_R_R::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bit 12 - Setting to 1 grants DBUS0 permission to write RTC FAST low address region."]
    #[inline(always)]
    pub fn pro_dram0_rtcfast_l_w(&self) -> PRO_DRAM0_RTCFAST_L_W_R {
        PRO_DRAM0_RTCFAST_L_W_R::new(((self.bits >> 12) & 1) != 0)
    }
    #[doc = "Bit 13 - Setting to 1 grants DBUS0 permission to read RTC FAST high address region."]
    #[inline(always)]
    pub fn pro_dram0_rtcfast_h_r(&self) -> PRO_DRAM0_RTCFAST_H_R_R {
        PRO_DRAM0_RTCFAST_H_R_R::new(((self.bits >> 13) & 1) != 0)
    }
    #[doc = "Bit 14 - Setting to 1 grants DBUS0 permission to write RTC FAST high address region."]
    #[inline(always)]
    pub fn pro_dram0_rtcfast_h_w(&self) -> PRO_DRAM0_RTCFAST_H_W_R {
        PRO_DRAM0_RTCFAST_H_W_R::new(((self.bits >> 14) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PRO_DRAM0_2")
            .field(
                "pro_dram0_rtcfast_spltaddr",
                &self.pro_dram0_rtcfast_spltaddr(),
            )
            .field("pro_dram0_rtcfast_l_r", &self.pro_dram0_rtcfast_l_r())
            .field("pro_dram0_rtcfast_l_w", &self.pro_dram0_rtcfast_l_w())
            .field("pro_dram0_rtcfast_h_r", &self.pro_dram0_rtcfast_h_r())
            .field("pro_dram0_rtcfast_h_w", &self.pro_dram0_rtcfast_h_w())
            .finish()
    }
}
impl W {
    #[doc = "Bits 0:10 - Configure the split address of RTC FAST for DBUS0 access."]
    #[inline(always)]
    pub fn pro_dram0_rtcfast_spltaddr(
        &mut self,
    ) -> PRO_DRAM0_RTCFAST_SPLTADDR_W<'_, PRO_DRAM0_2_SPEC> {
        PRO_DRAM0_RTCFAST_SPLTADDR_W::new(self, 0)
    }
    #[doc = "Bit 11 - Setting to 1 grants DBUS0 permission to read RTC FAST low address region."]
    #[inline(always)]
    pub fn pro_dram0_rtcfast_l_r(&mut self) -> PRO_DRAM0_RTCFAST_L_R_W<'_, PRO_DRAM0_2_SPEC> {
        PRO_DRAM0_RTCFAST_L_R_W::new(self, 11)
    }
    #[doc = "Bit 12 - Setting to 1 grants DBUS0 permission to write RTC FAST low address region."]
    #[inline(always)]
    pub fn pro_dram0_rtcfast_l_w(&mut self) -> PRO_DRAM0_RTCFAST_L_W_W<'_, PRO_DRAM0_2_SPEC> {
        PRO_DRAM0_RTCFAST_L_W_W::new(self, 12)
    }
    #[doc = "Bit 13 - Setting to 1 grants DBUS0 permission to read RTC FAST high address region."]
    #[inline(always)]
    pub fn pro_dram0_rtcfast_h_r(&mut self) -> PRO_DRAM0_RTCFAST_H_R_W<'_, PRO_DRAM0_2_SPEC> {
        PRO_DRAM0_RTCFAST_H_R_W::new(self, 13)
    }
    #[doc = "Bit 14 - Setting to 1 grants DBUS0 permission to write RTC FAST high address region."]
    #[inline(always)]
    pub fn pro_dram0_rtcfast_h_w(&mut self) -> PRO_DRAM0_RTCFAST_H_W_W<'_, PRO_DRAM0_2_SPEC> {
        PRO_DRAM0_RTCFAST_H_W_W::new(self, 14)
    }
}
#[doc = "DBUS permission control register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_dram0_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_dram0_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PRO_DRAM0_2_SPEC;
impl crate::RegisterSpec for PRO_DRAM0_2_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`pro_dram0_2::R`](R) reader structure"]
impl crate::Readable for PRO_DRAM0_2_SPEC {}
#[doc = "`write(|w| ..)` method takes [`pro_dram0_2::W`](W) writer structure"]
impl crate::Writable for PRO_DRAM0_2_SPEC {
    type Safety = crate::Unsafe;
}
#[doc = "`reset()` method sets PRO_DRAM0_2 to value 0x7800"]
impl crate::Resettable for PRO_DRAM0_2_SPEC {
    const RESET_VALUE: u32 = 0x7800;
}