Struct esp32s2::PMS

pub struct PMS { /* private fields */ }

Permissions Controller

Implementations

impl PMS

pub const PTR: *const RegisterBlock = {0x3f4c1000 as *const pms::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn sdio_0(&self) -> &SDIO_0

0x00 - SDIO permission control register 0.

pub fn sdio_1(&self) -> &SDIO_1

0x04 - SDIO permission control register 1.

pub fn mac_dump_0(&self) -> &MAC_DUMP_0

0x08 - MAC dump permission control register 0.

pub fn mac_dump_1(&self) -> &MAC_DUMP_1

0x0c - MAC dump permission control register 1.

pub fn pro_iram0_0(&self) -> &PRO_IRAM0_0

0x10 - IBUS permission control register 0.

pub fn pro_iram0_1(&self) -> &PRO_IRAM0_1

0x14 - IBUS permission control register 1.

pub fn pro_iram0_2(&self) -> &PRO_IRAM0_2

0x18 - IBUS permission control register 2.

pub fn pro_iram0_3(&self) -> &PRO_IRAM0_3

0x1c - IBUS permission control register 3.

pub fn pro_iram0_4(&self) -> &PRO_IRAM0_4

0x20 - IBUS permission control register 4.

pub fn pro_iram0_5(&self) -> &PRO_IRAM0_5

0x24 - IBUS status register.

pub fn pro_dram0_0(&self) -> &PRO_DRAM0_0

0x28 - DBUS permission control register 0.

pub fn pro_dram0_1(&self) -> &PRO_DRAM0_1

0x2c - DBUS permission control register 1.

pub fn pro_dram0_2(&self) -> &PRO_DRAM0_2

0x30 - DBUS permission control register 2.

pub fn pro_dram0_3(&self) -> &PRO_DRAM0_3

0x34 - DBUS permission control register 3.

pub fn pro_dram0_4(&self) -> &PRO_DRAM0_4

0x38 - DBUS status register.

pub fn pro_dport_0(&self) -> &PRO_DPORT_0

0x3c - PeriBus1 permission control register 0.

pub fn pro_dport_1(&self) -> &PRO_DPORT_1

0x40 - PeriBus1 permission control register 1.

pub fn pro_dport_2(&self) -> &PRO_DPORT_2

0x44 - PeriBus1 permission control register 2.

pub fn pro_dport_3(&self) -> &PRO_DPORT_3

0x48 - PeriBus1 permission control register 3.

pub fn pro_dport_4(&self) -> &PRO_DPORT_4

0x4c - PeriBus1 permission control register 4.

pub fn pro_dport_5(&self) -> &PRO_DPORT_5

0x50 - PeriBus1 permission control register 5.

pub fn pro_dport_6(&self) -> &PRO_DPORT_6

0x54 - PeriBus1 permission control register 6.

pub fn pro_dport_7(&self) -> &PRO_DPORT_7

0x58 - PeriBus1 status register.

pub fn pro_ahb_0(&self) -> &PRO_AHB_0

0x5c - PeriBus2 permission control register 0.

pub fn pro_ahb_1(&self) -> &PRO_AHB_1

0x60 - PeriBus2 permission control register 1.

pub fn pro_ahb_2(&self) -> &PRO_AHB_2

0x64 - PeriBus2 permission control register 2.

pub fn pro_ahb_3(&self) -> &PRO_AHB_3

0x68 - PeriBus2 permission control register 3.

pub fn pro_ahb_4(&self) -> &PRO_AHB_4

0x6c - PeriBus2 status register.

pub fn pro_trace_0(&self) -> &PRO_TRACE_0

0x70 - Trace memory permission control register 0.

pub fn pro_trace_1(&self) -> &PRO_TRACE_1

0x74 - Trace memory permission control register 1.

pub fn pro_cache_0(&self) -> &PRO_CACHE_0

0x78 - Cache permission control register 0.

pub fn pro_cache_1(&self) -> &PRO_CACHE_1

0x7c - Cache permission control register 1.

pub fn pro_cache_2(&self) -> &PRO_CACHE_2

0x80 - Cache permission control register 2.

pub fn pro_cache_3(&self) -> &PRO_CACHE_3

0x84 - Icache status register.

pub fn pro_cache_4(&self) -> &PRO_CACHE_4

0x88 - Dcache status register.

pub fn dma_apb_i_0(&self) -> &DMA_APB_I_0

0x8c - Internal DMA permission control register 0.

pub fn dma_apb_i_1(&self) -> &DMA_APB_I_1

0x90 - Internal DMA permission control register 1.

pub fn dma_apb_i_2(&self) -> &DMA_APB_I_2

0x94 - Internal DMA permission control register 2.

pub fn dma_apb_i_3(&self) -> &DMA_APB_I_3

0x98 - Internal DMA status register.

pub fn dma_rx_i_0(&self) -> &DMA_RX_I_0

0x9c - RX Copy DMA permission control register 0.

pub fn dma_rx_i_1(&self) -> &DMA_RX_I_1

0xa0 - RX Copy DMA permission control register 1.

pub fn dma_rx_i_2(&self) -> &DMA_RX_I_2

0xa4 - RX Copy DMA permission control register 2.

pub fn dma_rx_i_3(&self) -> &DMA_RX_I_3

0xa8 - RX Copy DMA status register.

pub fn dma_tx_i_0(&self) -> &DMA_TX_I_0

0xac - TX Copy DMA permission control register 0.

pub fn dma_tx_i_1(&self) -> &DMA_TX_I_1

0xb0 - TX Copy DMA permission control register 1.

pub fn dma_tx_i_2(&self) -> &DMA_TX_I_2

0xb4 - TX Copy DMA permission control register 2.

pub fn dma_tx_i_3(&self) -> &DMA_TX_I_3

0xb8 - TX Copy DMA status register.

pub fn pro_boot_location_0(&self) -> &PRO_BOOT_LOCATION_0

0xbc - Boot permission control register 0.

pub fn pro_boot_location_1(&self) -> &PRO_BOOT_LOCATION_1

0xc0 - Boot permission control register 1.

pub fn cache_source_0(&self) -> &CACHE_SOURCE_0

0xc4 - Cache access permission control register 0.

pub fn cache_source_1(&self) -> &CACHE_SOURCE_1

0xc8 - Cache access permission control register 1.

pub fn apb_peripheral_0(&self) -> &APB_PERIPHERAL_0

0xcc - Peripheral access permission control register 0.

pub fn apb_peripheral_1(&self) -> &APB_PERIPHERAL_1

0xd0 - Peripheral access permission control register 1.

pub fn occupy_0(&self) -> &OCCUPY_0

0xd4 - Occupy permission control register 0.

pub fn occupy_1(&self) -> &OCCUPY_1

0xd8 - Occupy permission control register 1.

pub fn occupy_2(&self) -> &OCCUPY_2

0xdc - Occupy permission control register 2.

pub fn occupy_3(&self) -> &OCCUPY_3

0xe0 - Occupy permission control register 3.

pub fn cache_tag_access_0(&self) -> &CACHE_TAG_ACCESS_0

0xe4 - Cache tag permission control register 0.

pub fn cache_tag_access_1(&self) -> &CACHE_TAG_ACCESS_1

0xe8 - Cache tag permission control register 1.

pub fn cache_mmu_access_0(&self) -> &CACHE_MMU_ACCESS_0

0xec - Cache MMU permission control register 0.

pub fn cache_mmu_access_1(&self) -> &CACHE_MMU_ACCESS_1

0xf0 - Cache MMU permission control register 1.

pub fn apb_peripheral_intr(&self) -> &APB_PERIPHERAL_INTR

0xf4 - PeribBus2 permission control register.

pub fn apb_peripheral_status(&self) -> &APB_PERIPHERAL_STATUS

0xf8 - PeribBus2 peripheral access status register.

pub fn cpu_peripheral_intr(&self) -> &CPU_PERIPHERAL_INTR

0xfc - PeribBus1 permission control register.

pub fn cpu_peripheral_status(&self) -> &CPU_PERIPHERAL_STATUS

0x100 - PeribBus1 peripheral access status register.

pub fn clock_gate(&self) -> &CLOCK_GATE

0x104 - Clock gate register of permission control.

pub fn date(&self) -> &DATE

0xffc - Version control register.

Trait Implementations

impl Debug for PMS

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for PMS

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for PMS