esp32p4/hp_sys_clkrst/
peri_clk_ctrl14.rs

1#[doc = "Register `PERI_CLK_CTRL14` reader"]
2pub type R = crate::R<PERI_CLK_CTRL14_SPEC>;
3#[doc = "Register `PERI_CLK_CTRL14` writer"]
4pub type W = crate::W<PERI_CLK_CTRL14_SPEC>;
5#[doc = "Field `I2S0_TX_DIV_Y` reader - Reserved"]
6pub type I2S0_TX_DIV_Y_R = crate::FieldReader<u16>;
7#[doc = "Field `I2S0_TX_DIV_Y` writer - Reserved"]
8pub type I2S0_TX_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
9#[doc = "Field `I2S0_TX_DIV_Z` reader - Reserved"]
10pub type I2S0_TX_DIV_Z_R = crate::FieldReader<u16>;
11#[doc = "Field `I2S0_TX_DIV_Z` writer - Reserved"]
12pub type I2S0_TX_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
13#[doc = "Field `I2S0_TX_DIV_YN1` reader - Reserved"]
14pub type I2S0_TX_DIV_YN1_R = crate::BitReader;
15#[doc = "Field `I2S0_TX_DIV_YN1` writer - Reserved"]
16pub type I2S0_TX_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `I2S0_MST_CLK_SEL` reader - Reserved"]
18pub type I2S0_MST_CLK_SEL_R = crate::BitReader;
19#[doc = "Field `I2S0_MST_CLK_SEL` writer - Reserved"]
20pub type I2S0_MST_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `I2S1_RX_CLK_EN` reader - Reserved"]
22pub type I2S1_RX_CLK_EN_R = crate::BitReader;
23#[doc = "Field `I2S1_RX_CLK_EN` writer - Reserved"]
24pub type I2S1_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `I2S1_RX_CLK_SRC_SEL` reader - Reserved"]
26pub type I2S1_RX_CLK_SRC_SEL_R = crate::FieldReader;
27#[doc = "Field `I2S1_RX_CLK_SRC_SEL` writer - Reserved"]
28pub type I2S1_RX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `I2S1_RX_DIV_N` reader - Reserved"]
30pub type I2S1_RX_DIV_N_R = crate::FieldReader;
31#[doc = "Field `I2S1_RX_DIV_N` writer - Reserved"]
32pub type I2S1_RX_DIV_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
33impl R {
34    #[doc = "Bits 0:8 - Reserved"]
35    #[inline(always)]
36    pub fn i2s0_tx_div_y(&self) -> I2S0_TX_DIV_Y_R {
37        I2S0_TX_DIV_Y_R::new((self.bits & 0x01ff) as u16)
38    }
39    #[doc = "Bits 9:17 - Reserved"]
40    #[inline(always)]
41    pub fn i2s0_tx_div_z(&self) -> I2S0_TX_DIV_Z_R {
42        I2S0_TX_DIV_Z_R::new(((self.bits >> 9) & 0x01ff) as u16)
43    }
44    #[doc = "Bit 18 - Reserved"]
45    #[inline(always)]
46    pub fn i2s0_tx_div_yn1(&self) -> I2S0_TX_DIV_YN1_R {
47        I2S0_TX_DIV_YN1_R::new(((self.bits >> 18) & 1) != 0)
48    }
49    #[doc = "Bit 19 - Reserved"]
50    #[inline(always)]
51    pub fn i2s0_mst_clk_sel(&self) -> I2S0_MST_CLK_SEL_R {
52        I2S0_MST_CLK_SEL_R::new(((self.bits >> 19) & 1) != 0)
53    }
54    #[doc = "Bit 20 - Reserved"]
55    #[inline(always)]
56    pub fn i2s1_rx_clk_en(&self) -> I2S1_RX_CLK_EN_R {
57        I2S1_RX_CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
58    }
59    #[doc = "Bits 21:22 - Reserved"]
60    #[inline(always)]
61    pub fn i2s1_rx_clk_src_sel(&self) -> I2S1_RX_CLK_SRC_SEL_R {
62        I2S1_RX_CLK_SRC_SEL_R::new(((self.bits >> 21) & 3) as u8)
63    }
64    #[doc = "Bits 23:30 - Reserved"]
65    #[inline(always)]
66    pub fn i2s1_rx_div_n(&self) -> I2S1_RX_DIV_N_R {
67        I2S1_RX_DIV_N_R::new(((self.bits >> 23) & 0xff) as u8)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("PERI_CLK_CTRL14")
74            .field(
75                "i2s0_tx_div_y",
76                &format_args!("{}", self.i2s0_tx_div_y().bits()),
77            )
78            .field(
79                "i2s0_tx_div_z",
80                &format_args!("{}", self.i2s0_tx_div_z().bits()),
81            )
82            .field(
83                "i2s0_tx_div_yn1",
84                &format_args!("{}", self.i2s0_tx_div_yn1().bit()),
85            )
86            .field(
87                "i2s0_mst_clk_sel",
88                &format_args!("{}", self.i2s0_mst_clk_sel().bit()),
89            )
90            .field(
91                "i2s1_rx_clk_en",
92                &format_args!("{}", self.i2s1_rx_clk_en().bit()),
93            )
94            .field(
95                "i2s1_rx_clk_src_sel",
96                &format_args!("{}", self.i2s1_rx_clk_src_sel().bits()),
97            )
98            .field(
99                "i2s1_rx_div_n",
100                &format_args!("{}", self.i2s1_rx_div_n().bits()),
101            )
102            .finish()
103    }
104}
105#[cfg(feature = "impl-register-debug")]
106impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL14_SPEC> {
107    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
108        core::fmt::Debug::fmt(&self.read(), f)
109    }
110}
111impl W {
112    #[doc = "Bits 0:8 - Reserved"]
113    #[inline(always)]
114    #[must_use]
115    pub fn i2s0_tx_div_y(&mut self) -> I2S0_TX_DIV_Y_W<PERI_CLK_CTRL14_SPEC> {
116        I2S0_TX_DIV_Y_W::new(self, 0)
117    }
118    #[doc = "Bits 9:17 - Reserved"]
119    #[inline(always)]
120    #[must_use]
121    pub fn i2s0_tx_div_z(&mut self) -> I2S0_TX_DIV_Z_W<PERI_CLK_CTRL14_SPEC> {
122        I2S0_TX_DIV_Z_W::new(self, 9)
123    }
124    #[doc = "Bit 18 - Reserved"]
125    #[inline(always)]
126    #[must_use]
127    pub fn i2s0_tx_div_yn1(&mut self) -> I2S0_TX_DIV_YN1_W<PERI_CLK_CTRL14_SPEC> {
128        I2S0_TX_DIV_YN1_W::new(self, 18)
129    }
130    #[doc = "Bit 19 - Reserved"]
131    #[inline(always)]
132    #[must_use]
133    pub fn i2s0_mst_clk_sel(&mut self) -> I2S0_MST_CLK_SEL_W<PERI_CLK_CTRL14_SPEC> {
134        I2S0_MST_CLK_SEL_W::new(self, 19)
135    }
136    #[doc = "Bit 20 - Reserved"]
137    #[inline(always)]
138    #[must_use]
139    pub fn i2s1_rx_clk_en(&mut self) -> I2S1_RX_CLK_EN_W<PERI_CLK_CTRL14_SPEC> {
140        I2S1_RX_CLK_EN_W::new(self, 20)
141    }
142    #[doc = "Bits 21:22 - Reserved"]
143    #[inline(always)]
144    #[must_use]
145    pub fn i2s1_rx_clk_src_sel(&mut self) -> I2S1_RX_CLK_SRC_SEL_W<PERI_CLK_CTRL14_SPEC> {
146        I2S1_RX_CLK_SRC_SEL_W::new(self, 21)
147    }
148    #[doc = "Bits 23:30 - Reserved"]
149    #[inline(always)]
150    #[must_use]
151    pub fn i2s1_rx_div_n(&mut self) -> I2S1_RX_DIV_N_W<PERI_CLK_CTRL14_SPEC> {
152        I2S1_RX_DIV_N_W::new(self, 23)
153    }
154}
155#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl14::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
156pub struct PERI_CLK_CTRL14_SPEC;
157impl crate::RegisterSpec for PERI_CLK_CTRL14_SPEC {
158    type Ux = u32;
159}
160#[doc = "`read()` method returns [`peri_clk_ctrl14::R`](R) reader structure"]
161impl crate::Readable for PERI_CLK_CTRL14_SPEC {}
162#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl14::W`](W) writer structure"]
163impl crate::Writable for PERI_CLK_CTRL14_SPEC {
164    type Safety = crate::Unsafe;
165    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
166    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
167}
168#[doc = "`reset()` method sets PERI_CLK_CTRL14 to value 0"]
169impl crate::Resettable for PERI_CLK_CTRL14_SPEC {
170    const RESET_VALUE: u32 = 0;
171}
esp32p4/hp_sys_clkrst/peri_clk_ctrl14.rs

esp32p4/hp_sys_clkrst/
peri_clk_ctrl14.rs
