esp32p4/spi3/
dout_mode.rs

1#[doc = "Register `DOUT_MODE` reader"]
2pub type R = crate::R<DOUT_MODE_SPEC>;
3#[doc = "Register `DOUT_MODE` writer"]
4pub type W = crate::W<DOUT_MODE_SPEC>;
5#[doc = "Field `DOUT0_MODE` reader - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
6pub type DOUT0_MODE_R = crate::BitReader;
7#[doc = "Field `DOUT0_MODE` writer - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
8pub type DOUT0_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DOUT1_MODE` reader - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
10pub type DOUT1_MODE_R = crate::BitReader;
11#[doc = "Field `DOUT1_MODE` writer - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
12pub type DOUT1_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DOUT2_MODE` reader - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
14pub type DOUT2_MODE_R = crate::BitReader;
15#[doc = "Field `DOUT2_MODE` writer - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
16pub type DOUT2_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DOUT3_MODE` reader - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
18pub type DOUT3_MODE_R = crate::BitReader;
19#[doc = "Field `DOUT3_MODE` writer - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
20pub type DOUT3_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
23    #[inline(always)]
24    pub fn dout0_mode(&self) -> DOUT0_MODE_R {
25        DOUT0_MODE_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
28    #[inline(always)]
29    pub fn dout1_mode(&self) -> DOUT1_MODE_R {
30        DOUT1_MODE_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
33    #[inline(always)]
34    pub fn dout2_mode(&self) -> DOUT2_MODE_R {
35        DOUT2_MODE_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
38    #[inline(always)]
39    pub fn dout3_mode(&self) -> DOUT3_MODE_R {
40        DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("DOUT_MODE")
47            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
48            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
49            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
50            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
51            .finish()
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
56    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
57        core::fmt::Debug::fmt(&self.read(), f)
58    }
59}
60impl W {
61    #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
62    #[inline(always)]
63    #[must_use]
64    pub fn dout0_mode(&mut self) -> DOUT0_MODE_W<DOUT_MODE_SPEC> {
65        DOUT0_MODE_W::new(self, 0)
66    }
67    #[doc = "Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
68    #[inline(always)]
69    #[must_use]
70    pub fn dout1_mode(&mut self) -> DOUT1_MODE_W<DOUT_MODE_SPEC> {
71        DOUT1_MODE_W::new(self, 1)
72    }
73    #[doc = "Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
74    #[inline(always)]
75    #[must_use]
76    pub fn dout2_mode(&mut self) -> DOUT2_MODE_W<DOUT_MODE_SPEC> {
77        DOUT2_MODE_W::new(self, 2)
78    }
79    #[doc = "Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
80    #[inline(always)]
81    #[must_use]
82    pub fn dout3_mode(&mut self) -> DOUT3_MODE_W<DOUT_MODE_SPEC> {
83        DOUT3_MODE_W::new(self, 3)
84    }
85}
86#[doc = "SPI output delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dout_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
87pub struct DOUT_MODE_SPEC;
88impl crate::RegisterSpec for DOUT_MODE_SPEC {
89    type Ux = u32;
90}
91#[doc = "`read()` method returns [`dout_mode::R`](R) reader structure"]
92impl crate::Readable for DOUT_MODE_SPEC {}
93#[doc = "`write(|w| ..)` method takes [`dout_mode::W`](W) writer structure"]
94impl crate::Writable for DOUT_MODE_SPEC {
95    type Safety = crate::Unsafe;
96    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
97    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
98}
99#[doc = "`reset()` method sets DOUT_MODE to value 0"]
100impl crate::Resettable for DOUT_MODE_SPEC {
101    const RESET_VALUE: u32 = 0;
102}
esp32p4/spi3/dout_mode.rs

esp32p4/spi3/
dout_mode.rs
