1#[doc = "Register `DIN_NUM` reader"]
2pub type R = crate::R<DIN_NUM_SPEC>;
3#[doc = "Register `DIN_NUM` writer"]
4pub type W = crate::W<DIN_NUM_SPEC>;
5#[doc = "Field `DIN0_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
6pub type DIN0_NUM_R = crate::FieldReader;
7#[doc = "Field `DIN0_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
8pub type DIN0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `DIN1_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
10pub type DIN1_NUM_R = crate::FieldReader;
11#[doc = "Field `DIN1_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
12pub type DIN1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `DIN2_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
14pub type DIN2_NUM_R = crate::FieldReader;
15#[doc = "Field `DIN2_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
16pub type DIN2_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `DIN3_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
18pub type DIN3_NUM_R = crate::FieldReader;
19#[doc = "Field `DIN3_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
20pub type DIN3_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `DIN4_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
22pub type DIN4_NUM_R = crate::FieldReader;
23#[doc = "Field `DIN4_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
24pub type DIN4_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `DIN5_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
26pub type DIN5_NUM_R = crate::FieldReader;
27#[doc = "Field `DIN5_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
28pub type DIN5_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `DIN6_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
30pub type DIN6_NUM_R = crate::FieldReader;
31#[doc = "Field `DIN6_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
32pub type DIN6_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `DIN7_NUM` reader - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
34pub type DIN7_NUM_R = crate::FieldReader;
35#[doc = "Field `DIN7_NUM` writer - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
36pub type DIN7_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37impl R {
38 #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
39 #[inline(always)]
40 pub fn din0_num(&self) -> DIN0_NUM_R {
41 DIN0_NUM_R::new((self.bits & 3) as u8)
42 }
43 #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
44 #[inline(always)]
45 pub fn din1_num(&self) -> DIN1_NUM_R {
46 DIN1_NUM_R::new(((self.bits >> 2) & 3) as u8)
47 }
48 #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
49 #[inline(always)]
50 pub fn din2_num(&self) -> DIN2_NUM_R {
51 DIN2_NUM_R::new(((self.bits >> 4) & 3) as u8)
52 }
53 #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
54 #[inline(always)]
55 pub fn din3_num(&self) -> DIN3_NUM_R {
56 DIN3_NUM_R::new(((self.bits >> 6) & 3) as u8)
57 }
58 #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
59 #[inline(always)]
60 pub fn din4_num(&self) -> DIN4_NUM_R {
61 DIN4_NUM_R::new(((self.bits >> 8) & 3) as u8)
62 }
63 #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
64 #[inline(always)]
65 pub fn din5_num(&self) -> DIN5_NUM_R {
66 DIN5_NUM_R::new(((self.bits >> 10) & 3) as u8)
67 }
68 #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
69 #[inline(always)]
70 pub fn din6_num(&self) -> DIN6_NUM_R {
71 DIN6_NUM_R::new(((self.bits >> 12) & 3) as u8)
72 }
73 #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
74 #[inline(always)]
75 pub fn din7_num(&self) -> DIN7_NUM_R {
76 DIN7_NUM_R::new(((self.bits >> 14) & 3) as u8)
77 }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for R {
81 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82 f.debug_struct("DIN_NUM")
83 .field("din0_num", &format_args!("{}", self.din0_num().bits()))
84 .field("din1_num", &format_args!("{}", self.din1_num().bits()))
85 .field("din2_num", &format_args!("{}", self.din2_num().bits()))
86 .field("din3_num", &format_args!("{}", self.din3_num().bits()))
87 .field("din4_num", &format_args!("{}", self.din4_num().bits()))
88 .field("din5_num", &format_args!("{}", self.din5_num().bits()))
89 .field("din6_num", &format_args!("{}", self.din6_num().bits()))
90 .field("din7_num", &format_args!("{}", self.din7_num().bits()))
91 .finish()
92 }
93}
94#[cfg(feature = "impl-register-debug")]
95impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
96 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
97 core::fmt::Debug::fmt(&self.read(), f)
98 }
99}
100impl W {
101 #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
102 #[inline(always)]
103 #[must_use]
104 pub fn din0_num(&mut self) -> DIN0_NUM_W<DIN_NUM_SPEC> {
105 DIN0_NUM_W::new(self, 0)
106 }
107 #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
108 #[inline(always)]
109 #[must_use]
110 pub fn din1_num(&mut self) -> DIN1_NUM_W<DIN_NUM_SPEC> {
111 DIN1_NUM_W::new(self, 2)
112 }
113 #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
114 #[inline(always)]
115 #[must_use]
116 pub fn din2_num(&mut self) -> DIN2_NUM_W<DIN_NUM_SPEC> {
117 DIN2_NUM_W::new(self, 4)
118 }
119 #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
120 #[inline(always)]
121 #[must_use]
122 pub fn din3_num(&mut self) -> DIN3_NUM_W<DIN_NUM_SPEC> {
123 DIN3_NUM_W::new(self, 6)
124 }
125 #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
126 #[inline(always)]
127 #[must_use]
128 pub fn din4_num(&mut self) -> DIN4_NUM_W<DIN_NUM_SPEC> {
129 DIN4_NUM_W::new(self, 8)
130 }
131 #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
132 #[inline(always)]
133 #[must_use]
134 pub fn din5_num(&mut self) -> DIN5_NUM_W<DIN_NUM_SPEC> {
135 DIN5_NUM_W::new(self, 10)
136 }
137 #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
138 #[inline(always)]
139 #[must_use]
140 pub fn din6_num(&mut self) -> DIN6_NUM_W<DIN_NUM_SPEC> {
141 DIN6_NUM_W::new(self, 12)
142 }
143 #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
144 #[inline(always)]
145 #[must_use]
146 pub fn din7_num(&mut self) -> DIN7_NUM_W<DIN_NUM_SPEC> {
147 DIN7_NUM_W::new(self, 14)
148 }
149}
150#[doc = "SPI input delay number configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din_num::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`din_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
151pub struct DIN_NUM_SPEC;
152impl crate::RegisterSpec for DIN_NUM_SPEC {
153 type Ux = u32;
154}
155#[doc = "`read()` method returns [`din_num::R`](R) reader structure"]
156impl crate::Readable for DIN_NUM_SPEC {}
157#[doc = "`write(|w| ..)` method takes [`din_num::W`](W) writer structure"]
158impl crate::Writable for DIN_NUM_SPEC {
159 type Safety = crate::Unsafe;
160 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
161 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162}
163#[doc = "`reset()` method sets DIN_NUM to value 0"]
164impl crate::Resettable for DIN_NUM_SPEC {
165 const RESET_VALUE: u32 = 0;
166}