esp32p4/mcpwm0/
clk.rs

1#[doc = "Register `CLK` reader"]
2pub type R = crate::R<CLK_SPEC>;
3#[doc = "Register `CLK` writer"]
4pub type W = crate::W<CLK_SPEC>;
5#[doc = "Field `EN` reader - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"]
6pub type EN_R = crate::BitReader;
7#[doc = "Field `EN` writer - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"]
8pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"]
11    #[inline(always)]
12    pub fn en(&self) -> EN_R {
13        EN_R::new((self.bits & 1) != 0)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("CLK")
20            .field("en", &format_args!("{}", self.en().bit()))
21            .finish()
22    }
23}
24#[cfg(feature = "impl-register-debug")]
25impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
26    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
27        core::fmt::Debug::fmt(&self.read(), f)
28    }
29}
30impl W {
31    #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"]
32    #[inline(always)]
33    #[must_use]
34    pub fn en(&mut self) -> EN_W<CLK_SPEC> {
35        EN_W::new(self, 0)
36    }
37}
38#[doc = "Global configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
39pub struct CLK_SPEC;
40impl crate::RegisterSpec for CLK_SPEC {
41    type Ux = u32;
42}
43#[doc = "`read()` method returns [`clk::R`](R) reader structure"]
44impl crate::Readable for CLK_SPEC {}
45#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"]
46impl crate::Writable for CLK_SPEC {
47    type Safety = crate::Unsafe;
48    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
49    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
50}
51#[doc = "`reset()` method sets CLK to value 0"]
52impl crate::Resettable for CLK_SPEC {
53    const RESET_VALUE: u32 = 0;
54}
esp32p4/mcpwm0/clk.rs

esp32p4/mcpwm0/
clk.rs
