esp32p4/spi0/
spi_smem_axi_addr_ctrl.rs

1#[doc = "Register `SPI_SMEM_AXI_ADDR_CTRL` reader"]
2pub type R = crate::R<SPI_SMEM_AXI_ADDR_CTRL_SPEC>;
3#[doc = "Field `ALL_FIFO_EMPTY` reader - The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others."]
4pub type ALL_FIFO_EMPTY_R = crate::BitReader;
5#[doc = "Field `SPI_RDATA_AFIFO_REMPTY` reader - 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending."]
6pub type SPI_RDATA_AFIFO_REMPTY_R = crate::BitReader;
7#[doc = "Field `SPI_RADDR_AFIFO_REMPTY` reader - 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending."]
8pub type SPI_RADDR_AFIFO_REMPTY_R = crate::BitReader;
9#[doc = "Field `SPI_WDATA_AFIFO_REMPTY` reader - 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending."]
10pub type SPI_WDATA_AFIFO_REMPTY_R = crate::BitReader;
11#[doc = "Field `SPI_WBLEN_AFIFO_REMPTY` reader - 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending."]
12pub type SPI_WBLEN_AFIFO_REMPTY_R = crate::BitReader;
13#[doc = "Field `SPI_ALL_AXI_TRANS_AFIFO_EMPTY` reader - This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE."]
14pub type SPI_ALL_AXI_TRANS_AFIFO_EMPTY_R = crate::BitReader;
15impl R {
16    #[doc = "Bit 26 - The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others."]
17    #[inline(always)]
18    pub fn all_fifo_empty(&self) -> ALL_FIFO_EMPTY_R {
19        ALL_FIFO_EMPTY_R::new(((self.bits >> 26) & 1) != 0)
20    }
21    #[doc = "Bit 27 - 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending."]
22    #[inline(always)]
23    pub fn spi_rdata_afifo_rempty(&self) -> SPI_RDATA_AFIFO_REMPTY_R {
24        SPI_RDATA_AFIFO_REMPTY_R::new(((self.bits >> 27) & 1) != 0)
25    }
26    #[doc = "Bit 28 - 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending."]
27    #[inline(always)]
28    pub fn spi_raddr_afifo_rempty(&self) -> SPI_RADDR_AFIFO_REMPTY_R {
29        SPI_RADDR_AFIFO_REMPTY_R::new(((self.bits >> 28) & 1) != 0)
30    }
31    #[doc = "Bit 29 - 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending."]
32    #[inline(always)]
33    pub fn spi_wdata_afifo_rempty(&self) -> SPI_WDATA_AFIFO_REMPTY_R {
34        SPI_WDATA_AFIFO_REMPTY_R::new(((self.bits >> 29) & 1) != 0)
35    }
36    #[doc = "Bit 30 - 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending."]
37    #[inline(always)]
38    pub fn spi_wblen_afifo_rempty(&self) -> SPI_WBLEN_AFIFO_REMPTY_R {
39        SPI_WBLEN_AFIFO_REMPTY_R::new(((self.bits >> 30) & 1) != 0)
40    }
41    #[doc = "Bit 31 - This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE."]
42    #[inline(always)]
43    pub fn spi_all_axi_trans_afifo_empty(&self) -> SPI_ALL_AXI_TRANS_AFIFO_EMPTY_R {
44        SPI_ALL_AXI_TRANS_AFIFO_EMPTY_R::new(((self.bits >> 31) & 1) != 0)
45    }
46}
47#[cfg(feature = "impl-register-debug")]
48impl core::fmt::Debug for R {
49    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
50        f.debug_struct("SPI_SMEM_AXI_ADDR_CTRL")
51            .field(
52                "all_fifo_empty",
53                &format_args!("{}", self.all_fifo_empty().bit()),
54            )
55            .field(
56                "spi_rdata_afifo_rempty",
57                &format_args!("{}", self.spi_rdata_afifo_rempty().bit()),
58            )
59            .field(
60                "spi_raddr_afifo_rempty",
61                &format_args!("{}", self.spi_raddr_afifo_rempty().bit()),
62            )
63            .field(
64                "spi_wdata_afifo_rempty",
65                &format_args!("{}", self.spi_wdata_afifo_rempty().bit()),
66            )
67            .field(
68                "spi_wblen_afifo_rempty",
69                &format_args!("{}", self.spi_wblen_afifo_rempty().bit()),
70            )
71            .field(
72                "spi_all_axi_trans_afifo_empty",
73                &format_args!("{}", self.spi_all_axi_trans_afifo_empty().bit()),
74            )
75            .finish()
76    }
77}
78#[cfg(feature = "impl-register-debug")]
79impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_AXI_ADDR_CTRL_SPEC> {
80    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
81        core::fmt::Debug::fmt(&self.read(), f)
82    }
83}
84#[doc = "SPI0 AXI address control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_axi_addr_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
85pub struct SPI_SMEM_AXI_ADDR_CTRL_SPEC;
86impl crate::RegisterSpec for SPI_SMEM_AXI_ADDR_CTRL_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [`spi_smem_axi_addr_ctrl::R`](R) reader structure"]
90impl crate::Readable for SPI_SMEM_AXI_ADDR_CTRL_SPEC {}
91#[doc = "`reset()` method sets SPI_SMEM_AXI_ADDR_CTRL to value 0xfc00_0000"]
92impl crate::Resettable for SPI_SMEM_AXI_ADDR_CTRL_SPEC {
93    const RESET_VALUE: u32 = 0xfc00_0000;
94}
esp32p4/spi0/spi_smem_axi_addr_ctrl.rs

esp32p4/spi0/
spi_smem_axi_addr_ctrl.rs
