esp32p4/lp_uart/
clkdiv_sync.rs

1#[doc = "Register `CLKDIV_SYNC` reader"]
2pub type R = crate::R<CLKDIV_SYNC_SPEC>;
3#[doc = "Register `CLKDIV_SYNC` writer"]
4pub type W = crate::W<CLKDIV_SYNC_SPEC>;
5#[doc = "Field `CLKDIV` reader - The integral part of the frequency divider factor."]
6pub type CLKDIV_R = crate::FieldReader<u16>;
7#[doc = "Field `CLKDIV` writer - The integral part of the frequency divider factor."]
8pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9#[doc = "Field `CLKDIV_FRAG` reader - The decimal part of the frequency divider factor."]
10pub type CLKDIV_FRAG_R = crate::FieldReader;
11#[doc = "Field `CLKDIV_FRAG` writer - The decimal part of the frequency divider factor."]
12pub type CLKDIV_FRAG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14    #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
15    #[inline(always)]
16    pub fn clkdiv(&self) -> CLKDIV_R {
17        CLKDIV_R::new((self.bits & 0x0fff) as u16)
18    }
19    #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."]
20    #[inline(always)]
21    pub fn clkdiv_frag(&self) -> CLKDIV_FRAG_R {
22        CLKDIV_FRAG_R::new(((self.bits >> 20) & 0x0f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CLKDIV_SYNC")
29            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
30            .field(
31                "clkdiv_frag",
32                &format_args!("{}", self.clkdiv_frag().bits()),
33            )
34            .finish()
35    }
36}
37#[cfg(feature = "impl-register-debug")]
38impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SYNC_SPEC> {
39    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
40        core::fmt::Debug::fmt(&self.read(), f)
41    }
42}
43impl W {
44    #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
45    #[inline(always)]
46    #[must_use]
47    pub fn clkdiv(&mut self) -> CLKDIV_W<CLKDIV_SYNC_SPEC> {
48        CLKDIV_W::new(self, 0)
49    }
50    #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."]
51    #[inline(always)]
52    #[must_use]
53    pub fn clkdiv_frag(&mut self) -> CLKDIV_FRAG_W<CLKDIV_SYNC_SPEC> {
54        CLKDIV_FRAG_W::new(self, 20)
55    }
56}
57#[doc = "Clock divider configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv_sync::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
58pub struct CLKDIV_SYNC_SPEC;
59impl crate::RegisterSpec for CLKDIV_SYNC_SPEC {
60    type Ux = u32;
61}
62#[doc = "`read()` method returns [`clkdiv_sync::R`](R) reader structure"]
63impl crate::Readable for CLKDIV_SYNC_SPEC {}
64#[doc = "`write(|w| ..)` method takes [`clkdiv_sync::W`](W) writer structure"]
65impl crate::Writable for CLKDIV_SYNC_SPEC {
66    type Safety = crate::Unsafe;
67    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
68    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
69}
70#[doc = "`reset()` method sets CLKDIV_SYNC to value 0x02b6"]
71impl crate::Resettable for CLKDIV_SYNC_SPEC {
72    const RESET_VALUE: u32 = 0x02b6;
73}
esp32p4/lp_uart/clkdiv_sync.rs

esp32p4/lp_uart/
clkdiv_sync.rs
