1#[doc = "Register `PERI_CLK_CTRL00` reader"]
2pub type R = crate::R<PERI_CLK_CTRL00_SPEC>;
3#[doc = "Register `PERI_CLK_CTRL00` writer"]
4pub type W = crate::W<PERI_CLK_CTRL00_SPEC>;
5#[doc = "Field `FLASH_CLK_SRC_SEL` reader - Reserved"]
6pub type FLASH_CLK_SRC_SEL_R = crate::FieldReader;
7#[doc = "Field `FLASH_CLK_SRC_SEL` writer - Reserved"]
8pub type FLASH_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `FLASH_PLL_CLK_EN` reader - Reserved"]
10pub type FLASH_PLL_CLK_EN_R = crate::BitReader;
11#[doc = "Field `FLASH_PLL_CLK_EN` writer - Reserved"]
12pub type FLASH_PLL_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FLASH_CORE_CLK_EN` reader - Reserved"]
14pub type FLASH_CORE_CLK_EN_R = crate::BitReader;
15#[doc = "Field `FLASH_CORE_CLK_EN` writer - Reserved"]
16pub type FLASH_CORE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FLASH_CORE_CLK_DIV_NUM` reader - Reserved"]
18pub type FLASH_CORE_CLK_DIV_NUM_R = crate::FieldReader;
19#[doc = "Field `FLASH_CORE_CLK_DIV_NUM` writer - Reserved"]
20pub type FLASH_CORE_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
21#[doc = "Field `PSRAM_CLK_SRC_SEL` reader - Reserved"]
22pub type PSRAM_CLK_SRC_SEL_R = crate::FieldReader;
23#[doc = "Field `PSRAM_CLK_SRC_SEL` writer - Reserved"]
24pub type PSRAM_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `PSRAM_PLL_CLK_EN` reader - Reserved"]
26pub type PSRAM_PLL_CLK_EN_R = crate::BitReader;
27#[doc = "Field `PSRAM_PLL_CLK_EN` writer - Reserved"]
28pub type PSRAM_PLL_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `PSRAM_CORE_CLK_EN` reader - Reserved"]
30pub type PSRAM_CORE_CLK_EN_R = crate::BitReader;
31#[doc = "Field `PSRAM_CORE_CLK_EN` writer - Reserved"]
32pub type PSRAM_CORE_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `PSRAM_CORE_CLK_DIV_NUM` reader - Reserved"]
34pub type PSRAM_CORE_CLK_DIV_NUM_R = crate::FieldReader;
35#[doc = "Field `PSRAM_CORE_CLK_DIV_NUM` writer - Reserved"]
36pub type PSRAM_CORE_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
37#[doc = "Field `PAD_EMAC_REF_CLK_EN` reader - Reserved"]
38pub type PAD_EMAC_REF_CLK_EN_R = crate::BitReader;
39#[doc = "Field `PAD_EMAC_REF_CLK_EN` writer - Reserved"]
40pub type PAD_EMAC_REF_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `EMAC_RMII_CLK_SRC_SEL` reader - Reserved"]
42pub type EMAC_RMII_CLK_SRC_SEL_R = crate::FieldReader;
43#[doc = "Field `EMAC_RMII_CLK_SRC_SEL` writer - Reserved"]
44pub type EMAC_RMII_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
45#[doc = "Field `EMAC_RMII_CLK_EN` reader - Reserved"]
46pub type EMAC_RMII_CLK_EN_R = crate::BitReader;
47#[doc = "Field `EMAC_RMII_CLK_EN` writer - Reserved"]
48pub type EMAC_RMII_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `EMAC_RX_CLK_SRC_SEL` reader - Reserved"]
50pub type EMAC_RX_CLK_SRC_SEL_R = crate::BitReader;
51#[doc = "Field `EMAC_RX_CLK_SRC_SEL` writer - Reserved"]
52pub type EMAC_RX_CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `EMAC_RX_CLK_EN` reader - Reserved"]
54pub type EMAC_RX_CLK_EN_R = crate::BitReader;
55#[doc = "Field `EMAC_RX_CLK_EN` writer - Reserved"]
56pub type EMAC_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58 #[doc = "Bits 0:1 - Reserved"]
59 #[inline(always)]
60 pub fn flash_clk_src_sel(&self) -> FLASH_CLK_SRC_SEL_R {
61 FLASH_CLK_SRC_SEL_R::new((self.bits & 3) as u8)
62 }
63 #[doc = "Bit 2 - Reserved"]
64 #[inline(always)]
65 pub fn flash_pll_clk_en(&self) -> FLASH_PLL_CLK_EN_R {
66 FLASH_PLL_CLK_EN_R::new(((self.bits >> 2) & 1) != 0)
67 }
68 #[doc = "Bit 3 - Reserved"]
69 #[inline(always)]
70 pub fn flash_core_clk_en(&self) -> FLASH_CORE_CLK_EN_R {
71 FLASH_CORE_CLK_EN_R::new(((self.bits >> 3) & 1) != 0)
72 }
73 #[doc = "Bits 4:11 - Reserved"]
74 #[inline(always)]
75 pub fn flash_core_clk_div_num(&self) -> FLASH_CORE_CLK_DIV_NUM_R {
76 FLASH_CORE_CLK_DIV_NUM_R::new(((self.bits >> 4) & 0xff) as u8)
77 }
78 #[doc = "Bits 12:13 - Reserved"]
79 #[inline(always)]
80 pub fn psram_clk_src_sel(&self) -> PSRAM_CLK_SRC_SEL_R {
81 PSRAM_CLK_SRC_SEL_R::new(((self.bits >> 12) & 3) as u8)
82 }
83 #[doc = "Bit 14 - Reserved"]
84 #[inline(always)]
85 pub fn psram_pll_clk_en(&self) -> PSRAM_PLL_CLK_EN_R {
86 PSRAM_PLL_CLK_EN_R::new(((self.bits >> 14) & 1) != 0)
87 }
88 #[doc = "Bit 15 - Reserved"]
89 #[inline(always)]
90 pub fn psram_core_clk_en(&self) -> PSRAM_CORE_CLK_EN_R {
91 PSRAM_CORE_CLK_EN_R::new(((self.bits >> 15) & 1) != 0)
92 }
93 #[doc = "Bits 16:23 - Reserved"]
94 #[inline(always)]
95 pub fn psram_core_clk_div_num(&self) -> PSRAM_CORE_CLK_DIV_NUM_R {
96 PSRAM_CORE_CLK_DIV_NUM_R::new(((self.bits >> 16) & 0xff) as u8)
97 }
98 #[doc = "Bit 24 - Reserved"]
99 #[inline(always)]
100 pub fn pad_emac_ref_clk_en(&self) -> PAD_EMAC_REF_CLK_EN_R {
101 PAD_EMAC_REF_CLK_EN_R::new(((self.bits >> 24) & 1) != 0)
102 }
103 #[doc = "Bits 25:26 - Reserved"]
104 #[inline(always)]
105 pub fn emac_rmii_clk_src_sel(&self) -> EMAC_RMII_CLK_SRC_SEL_R {
106 EMAC_RMII_CLK_SRC_SEL_R::new(((self.bits >> 25) & 3) as u8)
107 }
108 #[doc = "Bit 27 - Reserved"]
109 #[inline(always)]
110 pub fn emac_rmii_clk_en(&self) -> EMAC_RMII_CLK_EN_R {
111 EMAC_RMII_CLK_EN_R::new(((self.bits >> 27) & 1) != 0)
112 }
113 #[doc = "Bit 28 - Reserved"]
114 #[inline(always)]
115 pub fn emac_rx_clk_src_sel(&self) -> EMAC_RX_CLK_SRC_SEL_R {
116 EMAC_RX_CLK_SRC_SEL_R::new(((self.bits >> 28) & 1) != 0)
117 }
118 #[doc = "Bit 29 - Reserved"]
119 #[inline(always)]
120 pub fn emac_rx_clk_en(&self) -> EMAC_RX_CLK_EN_R {
121 EMAC_RX_CLK_EN_R::new(((self.bits >> 29) & 1) != 0)
122 }
123}
124#[cfg(feature = "impl-register-debug")]
125impl core::fmt::Debug for R {
126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
127 f.debug_struct("PERI_CLK_CTRL00")
128 .field(
129 "flash_clk_src_sel",
130 &format_args!("{}", self.flash_clk_src_sel().bits()),
131 )
132 .field(
133 "flash_pll_clk_en",
134 &format_args!("{}", self.flash_pll_clk_en().bit()),
135 )
136 .field(
137 "flash_core_clk_en",
138 &format_args!("{}", self.flash_core_clk_en().bit()),
139 )
140 .field(
141 "flash_core_clk_div_num",
142 &format_args!("{}", self.flash_core_clk_div_num().bits()),
143 )
144 .field(
145 "psram_clk_src_sel",
146 &format_args!("{}", self.psram_clk_src_sel().bits()),
147 )
148 .field(
149 "psram_pll_clk_en",
150 &format_args!("{}", self.psram_pll_clk_en().bit()),
151 )
152 .field(
153 "psram_core_clk_en",
154 &format_args!("{}", self.psram_core_clk_en().bit()),
155 )
156 .field(
157 "psram_core_clk_div_num",
158 &format_args!("{}", self.psram_core_clk_div_num().bits()),
159 )
160 .field(
161 "pad_emac_ref_clk_en",
162 &format_args!("{}", self.pad_emac_ref_clk_en().bit()),
163 )
164 .field(
165 "emac_rmii_clk_src_sel",
166 &format_args!("{}", self.emac_rmii_clk_src_sel().bits()),
167 )
168 .field(
169 "emac_rmii_clk_en",
170 &format_args!("{}", self.emac_rmii_clk_en().bit()),
171 )
172 .field(
173 "emac_rx_clk_src_sel",
174 &format_args!("{}", self.emac_rx_clk_src_sel().bit()),
175 )
176 .field(
177 "emac_rx_clk_en",
178 &format_args!("{}", self.emac_rx_clk_en().bit()),
179 )
180 .finish()
181 }
182}
183#[cfg(feature = "impl-register-debug")]
184impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL00_SPEC> {
185 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
186 core::fmt::Debug::fmt(&self.read(), f)
187 }
188}
189impl W {
190 #[doc = "Bits 0:1 - Reserved"]
191 #[inline(always)]
192 #[must_use]
193 pub fn flash_clk_src_sel(&mut self) -> FLASH_CLK_SRC_SEL_W<PERI_CLK_CTRL00_SPEC> {
194 FLASH_CLK_SRC_SEL_W::new(self, 0)
195 }
196 #[doc = "Bit 2 - Reserved"]
197 #[inline(always)]
198 #[must_use]
199 pub fn flash_pll_clk_en(&mut self) -> FLASH_PLL_CLK_EN_W<PERI_CLK_CTRL00_SPEC> {
200 FLASH_PLL_CLK_EN_W::new(self, 2)
201 }
202 #[doc = "Bit 3 - Reserved"]
203 #[inline(always)]
204 #[must_use]
205 pub fn flash_core_clk_en(&mut self) -> FLASH_CORE_CLK_EN_W<PERI_CLK_CTRL00_SPEC> {
206 FLASH_CORE_CLK_EN_W::new(self, 3)
207 }
208 #[doc = "Bits 4:11 - Reserved"]
209 #[inline(always)]
210 #[must_use]
211 pub fn flash_core_clk_div_num(&mut self) -> FLASH_CORE_CLK_DIV_NUM_W<PERI_CLK_CTRL00_SPEC> {
212 FLASH_CORE_CLK_DIV_NUM_W::new(self, 4)
213 }
214 #[doc = "Bits 12:13 - Reserved"]
215 #[inline(always)]
216 #[must_use]
217 pub fn psram_clk_src_sel(&mut self) -> PSRAM_CLK_SRC_SEL_W<PERI_CLK_CTRL00_SPEC> {
218 PSRAM_CLK_SRC_SEL_W::new(self, 12)
219 }
220 #[doc = "Bit 14 - Reserved"]
221 #[inline(always)]
222 #[must_use]
223 pub fn psram_pll_clk_en(&mut self) -> PSRAM_PLL_CLK_EN_W<PERI_CLK_CTRL00_SPEC> {
224 PSRAM_PLL_CLK_EN_W::new(self, 14)
225 }
226 #[doc = "Bit 15 - Reserved"]
227 #[inline(always)]
228 #[must_use]
229 pub fn psram_core_clk_en(&mut self) -> PSRAM_CORE_CLK_EN_W<PERI_CLK_CTRL00_SPEC> {
230 PSRAM_CORE_CLK_EN_W::new(self, 15)
231 }
232 #[doc = "Bits 16:23 - Reserved"]
233 #[inline(always)]
234 #[must_use]
235 pub fn psram_core_clk_div_num(&mut self) -> PSRAM_CORE_CLK_DIV_NUM_W<PERI_CLK_CTRL00_SPEC> {
236 PSRAM_CORE_CLK_DIV_NUM_W::new(self, 16)
237 }
238 #[doc = "Bit 24 - Reserved"]
239 #[inline(always)]
240 #[must_use]
241 pub fn pad_emac_ref_clk_en(&mut self) -> PAD_EMAC_REF_CLK_EN_W<PERI_CLK_CTRL00_SPEC> {
242 PAD_EMAC_REF_CLK_EN_W::new(self, 24)
243 }
244 #[doc = "Bits 25:26 - Reserved"]
245 #[inline(always)]
246 #[must_use]
247 pub fn emac_rmii_clk_src_sel(&mut self) -> EMAC_RMII_CLK_SRC_SEL_W<PERI_CLK_CTRL00_SPEC> {
248 EMAC_RMII_CLK_SRC_SEL_W::new(self, 25)
249 }
250 #[doc = "Bit 27 - Reserved"]
251 #[inline(always)]
252 #[must_use]
253 pub fn emac_rmii_clk_en(&mut self) -> EMAC_RMII_CLK_EN_W<PERI_CLK_CTRL00_SPEC> {
254 EMAC_RMII_CLK_EN_W::new(self, 27)
255 }
256 #[doc = "Bit 28 - Reserved"]
257 #[inline(always)]
258 #[must_use]
259 pub fn emac_rx_clk_src_sel(&mut self) -> EMAC_RX_CLK_SRC_SEL_W<PERI_CLK_CTRL00_SPEC> {
260 EMAC_RX_CLK_SRC_SEL_W::new(self, 28)
261 }
262 #[doc = "Bit 29 - Reserved"]
263 #[inline(always)]
264 #[must_use]
265 pub fn emac_rx_clk_en(&mut self) -> EMAC_RX_CLK_EN_W<PERI_CLK_CTRL00_SPEC> {
266 EMAC_RX_CLK_EN_W::new(self, 29)
267 }
268}
269#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl00::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl00::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
270pub struct PERI_CLK_CTRL00_SPEC;
271impl crate::RegisterSpec for PERI_CLK_CTRL00_SPEC {
272 type Ux = u32;
273}
274#[doc = "`read()` method returns [`peri_clk_ctrl00::R`](R) reader structure"]
275impl crate::Readable for PERI_CLK_CTRL00_SPEC {}
276#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl00::W`](W) writer structure"]
277impl crate::Writable for PERI_CLK_CTRL00_SPEC {
278 type Safety = crate::Unsafe;
279 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
280 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
281}
282#[doc = "`reset()` method sets PERI_CLK_CTRL00 to value 0xc03c"]
283impl crate::Resettable for PERI_CLK_CTRL00_SPEC {
284 const RESET_VALUE: u32 = 0xc03c;
285}