esp32p4-0.2.0
Platform
Feature flags

docs.rs

Rust

esp32p4 0.2.0

Peripheral access crate for the ESP32-P4

Crate
Source
Builds
Feature flags

..
clock_gate.rs
date.rs
l1_bypass_cache_conf.rs
l1_cache_acs_cnt_ctrl.rs
l1_cache_acs_cnt_int_clr.rs
l1_cache_acs_cnt_int_ena.rs
l1_cache_acs_cnt_int_raw.rs
l1_cache_acs_cnt_int_st.rs
l1_cache_acs_fail_ctrl.rs
l1_cache_acs_fail_int_clr.rs
l1_cache_acs_fail_int_ena.rs
l1_cache_acs_fail_int_raw.rs
l1_cache_acs_fail_int_st.rs
l1_cache_atomic_conf.rs
l1_cache_autoload_buf_clr_ctrl.rs
l1_cache_data_mem_acs_conf.rs
l1_cache_data_mem_power_ctrl.rs
l1_cache_debug_bus.rs
l1_cache_freeze_ctrl.rs
l1_cache_object_ctrl.rs
l1_cache_preload_rst_ctrl.rs
l1_cache_sync_rst_ctrl.rs
l1_cache_tag_mem_acs_conf.rs
l1_cache_tag_mem_power_ctrl.rs
l1_cache_vaddr.rs
l1_cache_way_object.rs
l1_cache_wrap_around_ctrl.rs
l1_dbus0_acs_conflict_cnt.rs
l1_dbus0_acs_hit_cnt.rs
l1_dbus0_acs_miss_cnt.rs
l1_dbus0_acs_nxtlvl_rd_cnt.rs
l1_dbus0_acs_nxtlvl_wr_cnt.rs
l1_dbus1_acs_conflict_cnt.rs
l1_dbus1_acs_hit_cnt.rs
l1_dbus1_acs_miss_cnt.rs
l1_dbus1_acs_nxtlvl_rd_cnt.rs
l1_dbus1_acs_nxtlvl_wr_cnt.rs
l1_dbus2_acs_conflict_cnt.rs
l1_dbus2_acs_hit_cnt.rs
l1_dbus2_acs_miss_cnt.rs
l1_dbus2_acs_nxtlvl_rd_cnt.rs
l1_dbus2_acs_nxtlvl_wr_cnt.rs
l1_dbus3_acs_conflict_cnt.rs
l1_dbus3_acs_hit_cnt.rs
l1_dbus3_acs_miss_cnt.rs
l1_dbus3_acs_nxtlvl_rd_cnt.rs
l1_dbus3_acs_nxtlvl_wr_cnt.rs
l1_dcache_acs_fail_addr.rs
l1_dcache_acs_fail_id_attr.rs
l1_dcache_autoload_ctrl.rs
l1_dcache_autoload_sct0_addr.rs
l1_dcache_autoload_sct0_size.rs
l1_dcache_autoload_sct1_addr.rs
l1_dcache_autoload_sct1_size.rs
l1_dcache_autoload_sct2_addr.rs
l1_dcache_autoload_sct2_size.rs
l1_dcache_autoload_sct3_addr.rs
l1_dcache_autoload_sct3_size.rs
l1_dcache_blocksize_conf.rs
l1_dcache_cachesize_conf.rs
l1_dcache_ctrl.rs
l1_dcache_preload_addr.rs
l1_dcache_preload_ctrl.rs
l1_dcache_preload_size.rs
l1_dcache_prelock_conf.rs
l1_dcache_prelock_sct0_addr.rs
l1_dcache_prelock_sct1_addr.rs
l1_dcache_prelock_sct_size.rs
l1_ibus0_acs_conflict_cnt.rs
l1_ibus0_acs_hit_cnt.rs
l1_ibus0_acs_miss_cnt.rs
l1_ibus0_acs_nxtlvl_rd_cnt.rs
l1_ibus1_acs_conflict_cnt.rs
l1_ibus1_acs_hit_cnt.rs
l1_ibus1_acs_miss_cnt.rs
l1_ibus1_acs_nxtlvl_rd_cnt.rs
l1_ibus2_acs_conflict_cnt.rs
l1_ibus2_acs_hit_cnt.rs
l1_ibus2_acs_miss_cnt.rs
l1_ibus2_acs_nxtlvl_rd_cnt.rs
l1_ibus3_acs_conflict_cnt.rs
l1_ibus3_acs_hit_cnt.rs
l1_ibus3_acs_miss_cnt.rs
l1_ibus3_acs_nxtlvl_rd_cnt.rs
l1_icache0_acs_fail_addr.rs
l1_icache0_acs_fail_id_attr.rs
l1_icache0_autoload_ctrl.rs
l1_icache0_autoload_sct0_addr.rs
l1_icache0_autoload_sct0_size.rs
l1_icache0_autoload_sct1_addr.rs
l1_icache0_autoload_sct1_size.rs
l1_icache0_preload_addr.rs
l1_icache0_preload_ctrl.rs
l1_icache0_preload_size.rs
l1_icache0_prelock_conf.rs
l1_icache0_prelock_sct0_addr.rs
l1_icache0_prelock_sct1_addr.rs
l1_icache0_prelock_sct_size.rs
l1_icache1_acs_fail_addr.rs
l1_icache1_acs_fail_id_attr.rs
l1_icache1_autoload_ctrl.rs
l1_icache1_autoload_sct0_addr.rs
l1_icache1_autoload_sct0_size.rs
l1_icache1_autoload_sct1_addr.rs
l1_icache1_autoload_sct1_size.rs
l1_icache1_preload_addr.rs
l1_icache1_preload_ctrl.rs
l1_icache1_preload_size.rs
l1_icache1_prelock_conf.rs
l1_icache1_prelock_sct0_addr.rs
l1_icache1_prelock_sct1_addr.rs
l1_icache1_prelock_sct_size.rs
l1_icache2_acs_fail_addr.rs
l1_icache2_acs_fail_id_attr.rs
l1_icache2_autoload_ctrl.rs
l1_icache2_autoload_sct0_addr.rs
l1_icache2_autoload_sct0_size.rs
l1_icache2_autoload_sct1_addr.rs
l1_icache2_autoload_sct1_size.rs
l1_icache2_preload_addr.rs
l1_icache2_preload_ctrl.rs
l1_icache2_preload_size.rs
l1_icache2_prelock_conf.rs
l1_icache2_prelock_sct0_addr.rs
l1_icache2_prelock_sct1_addr.rs
l1_icache2_prelock_sct_size.rs
l1_icache3_acs_fail_addr.rs
l1_icache3_acs_fail_id_attr.rs
l1_icache3_autoload_ctrl.rs
l1_icache3_autoload_sct0_addr.rs
l1_icache3_autoload_sct0_size.rs
l1_icache3_autoload_sct1_addr.rs
l1_icache3_autoload_sct1_size.rs
l1_icache3_preload_addr.rs
l1_icache3_preload_ctrl.rs
l1_icache3_preload_size.rs
l1_icache3_prelock_conf.rs
l1_icache3_prelock_sct0_addr.rs
l1_icache3_prelock_sct1_addr.rs
l1_icache3_prelock_sct_size.rs
l1_icache_blocksize_conf.rs
l1_icache_cachesize_conf.rs
l1_icache_ctrl.rs
l1_unallocate_buffer_clear.rs
l2_bypass_cache_conf.rs
l2_cache_access_attr_ctrl.rs
l2_cache_acs_cnt_ctrl.rs
l2_cache_acs_cnt_int_clr.rs
l2_cache_acs_cnt_int_ena.rs
l2_cache_acs_cnt_int_raw.rs
l2_cache_acs_cnt_int_st.rs
l2_cache_acs_fail_addr.rs
l2_cache_acs_fail_ctrl.rs
l2_cache_acs_fail_id_attr.rs
l2_cache_acs_fail_int_clr.rs
l2_cache_acs_fail_int_ena.rs
l2_cache_acs_fail_int_raw.rs
l2_cache_acs_fail_int_st.rs
l2_cache_autoload_buf_clr_ctrl.rs
l2_cache_autoload_ctrl.rs
l2_cache_autoload_sct0_addr.rs
l2_cache_autoload_sct0_size.rs
l2_cache_autoload_sct1_addr.rs
l2_cache_autoload_sct1_size.rs
l2_cache_autoload_sct2_addr.rs
l2_cache_autoload_sct2_size.rs
l2_cache_autoload_sct3_addr.rs
l2_cache_autoload_sct3_size.rs
l2_cache_blocksize_conf.rs
l2_cache_cachesize_conf.rs
l2_cache_ctrl.rs
l2_cache_data_mem_acs_conf.rs
l2_cache_data_mem_power_ctrl.rs
l2_cache_debug_bus.rs
l2_cache_freeze_ctrl.rs
l2_cache_object_ctrl.rs
l2_cache_preload_addr.rs
l2_cache_preload_ctrl.rs
l2_cache_preload_rst_ctrl.rs
l2_cache_preload_size.rs
l2_cache_prelock_conf.rs
l2_cache_prelock_sct0_addr.rs
l2_cache_prelock_sct1_addr.rs
l2_cache_prelock_sct_size.rs
l2_cache_sync_preload_exception.rs
l2_cache_sync_preload_int_clr.rs
l2_cache_sync_preload_int_ena.rs
l2_cache_sync_preload_int_raw.rs
l2_cache_sync_preload_int_st.rs
l2_cache_sync_rst_ctrl.rs
l2_cache_tag_mem_acs_conf.rs
l2_cache_tag_mem_power_ctrl.rs
l2_cache_vaddr.rs
l2_cache_way_object.rs
l2_cache_wrap_around_ctrl.rs
l2_dbus0_acs_conflict_cnt.rs
l2_dbus0_acs_hit_cnt.rs
l2_dbus0_acs_miss_cnt.rs
l2_dbus0_acs_nxtlvl_rd_cnt.rs
l2_dbus0_acs_nxtlvl_wr_cnt.rs
l2_dbus1_acs_conflict_cnt.rs
l2_dbus1_acs_hit_cnt.rs
l2_dbus1_acs_miss_cnt.rs
l2_dbus1_acs_nxtlvl_rd_cnt.rs
l2_dbus1_acs_nxtlvl_wr_cnt.rs
l2_dbus2_acs_conflict_cnt.rs
l2_dbus2_acs_hit_cnt.rs
l2_dbus2_acs_miss_cnt.rs
l2_dbus2_acs_nxtlvl_rd_cnt.rs
l2_dbus2_acs_nxtlvl_wr_cnt.rs
l2_dbus3_acs_conflict_cnt.rs
l2_dbus3_acs_hit_cnt.rs
l2_dbus3_acs_miss_cnt.rs
l2_dbus3_acs_nxtlvl_rd_cnt.rs
l2_dbus3_acs_nxtlvl_wr_cnt.rs
l2_ibus0_acs_conflict_cnt.rs
l2_ibus0_acs_hit_cnt.rs
l2_ibus0_acs_miss_cnt.rs
l2_ibus0_acs_nxtlvl_rd_cnt.rs
l2_ibus1_acs_conflict_cnt.rs
l2_ibus1_acs_hit_cnt.rs
l2_ibus1_acs_miss_cnt.rs
l2_ibus1_acs_nxtlvl_rd_cnt.rs
l2_ibus2_acs_conflict_cnt.rs
l2_ibus2_acs_hit_cnt.rs
l2_ibus2_acs_miss_cnt.rs
l2_ibus2_acs_nxtlvl_rd_cnt.rs
l2_ibus3_acs_conflict_cnt.rs
l2_ibus3_acs_hit_cnt.rs
l2_ibus3_acs_miss_cnt.rs
l2_ibus3_acs_nxtlvl_rd_cnt.rs
l2_unallocate_buffer_clear.rs
level_split0.rs
level_split1.rs
lock_addr.rs
lock_ctrl.rs
lock_map.rs
lock_size.rs
redundancy_sig0.rs
redundancy_sig1.rs
redundancy_sig2.rs
redundancy_sig3.rs
redundancy_sig4.rs
sync_addr.rs
sync_ctrl.rs
sync_l1_cache_preload_exception.rs
sync_l1_cache_preload_int_clr.rs
sync_l1_cache_preload_int_ena.rs
sync_l1_cache_preload_int_raw.rs
sync_l1_cache_preload_int_st.rs
sync_map.rs
sync_size.rs