esp32p4/lp_sys/
rng_cfg.rs

1#[doc = "Register `RNG_CFG` reader"]
2pub type R = crate::R<RNG_CFG_SPEC>;
3#[doc = "Register `RNG_CFG` writer"]
4pub type W = crate::W<RNG_CFG_SPEC>;
5#[doc = "Field `RNG_TIMER_EN` reader - enable rng timer"]
6pub type RNG_TIMER_EN_R = crate::BitReader;
7#[doc = "Field `RNG_TIMER_EN` writer - enable rng timer"]
8pub type RNG_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RNG_TIMER_PSCALE` reader - configure ng timer pscale"]
10pub type RNG_TIMER_PSCALE_R = crate::FieldReader;
11#[doc = "Field `RNG_TIMER_PSCALE` writer - configure ng timer pscale"]
12pub type RNG_TIMER_PSCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `RNG_SAR_ENABLE` reader - enable rng_saradc"]
14pub type RNG_SAR_ENABLE_R = crate::BitReader;
15#[doc = "Field `RNG_SAR_ENABLE` writer - enable rng_saradc"]
16pub type RNG_SAR_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RNG_SAR_DATA` reader - debug rng sar sample cnt"]
18pub type RNG_SAR_DATA_R = crate::FieldReader<u16>;
19impl R {
20    #[doc = "Bit 0 - enable rng timer"]
21    #[inline(always)]
22    pub fn rng_timer_en(&self) -> RNG_TIMER_EN_R {
23        RNG_TIMER_EN_R::new((self.bits & 1) != 0)
24    }
25    #[doc = "Bits 1:8 - configure ng timer pscale"]
26    #[inline(always)]
27    pub fn rng_timer_pscale(&self) -> RNG_TIMER_PSCALE_R {
28        RNG_TIMER_PSCALE_R::new(((self.bits >> 1) & 0xff) as u8)
29    }
30    #[doc = "Bit 9 - enable rng_saradc"]
31    #[inline(always)]
32    pub fn rng_sar_enable(&self) -> RNG_SAR_ENABLE_R {
33        RNG_SAR_ENABLE_R::new(((self.bits >> 9) & 1) != 0)
34    }
35    #[doc = "Bits 16:28 - debug rng sar sample cnt"]
36    #[inline(always)]
37    pub fn rng_sar_data(&self) -> RNG_SAR_DATA_R {
38        RNG_SAR_DATA_R::new(((self.bits >> 16) & 0x1fff) as u16)
39    }
40}
41#[cfg(feature = "impl-register-debug")]
42impl core::fmt::Debug for R {
43    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
44        f.debug_struct("RNG_CFG")
45            .field(
46                "rng_timer_en",
47                &format_args!("{}", self.rng_timer_en().bit()),
48            )
49            .field(
50                "rng_timer_pscale",
51                &format_args!("{}", self.rng_timer_pscale().bits()),
52            )
53            .field(
54                "rng_sar_enable",
55                &format_args!("{}", self.rng_sar_enable().bit()),
56            )
57            .field(
58                "rng_sar_data",
59                &format_args!("{}", self.rng_sar_data().bits()),
60            )
61            .finish()
62    }
63}
64#[cfg(feature = "impl-register-debug")]
65impl core::fmt::Debug for crate::generic::Reg<RNG_CFG_SPEC> {
66    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
67        core::fmt::Debug::fmt(&self.read(), f)
68    }
69}
70impl W {
71    #[doc = "Bit 0 - enable rng timer"]
72    #[inline(always)]
73    #[must_use]
74    pub fn rng_timer_en(&mut self) -> RNG_TIMER_EN_W<RNG_CFG_SPEC> {
75        RNG_TIMER_EN_W::new(self, 0)
76    }
77    #[doc = "Bits 1:8 - configure ng timer pscale"]
78    #[inline(always)]
79    #[must_use]
80    pub fn rng_timer_pscale(&mut self) -> RNG_TIMER_PSCALE_W<RNG_CFG_SPEC> {
81        RNG_TIMER_PSCALE_W::new(self, 1)
82    }
83    #[doc = "Bit 9 - enable rng_saradc"]
84    #[inline(always)]
85    #[must_use]
86    pub fn rng_sar_enable(&mut self) -> RNG_SAR_ENABLE_W<RNG_CFG_SPEC> {
87        RNG_SAR_ENABLE_W::new(self, 9)
88    }
89}
90#[doc = "rng cfg register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
91pub struct RNG_CFG_SPEC;
92impl crate::RegisterSpec for RNG_CFG_SPEC {
93    type Ux = u32;
94}
95#[doc = "`read()` method returns [`rng_cfg::R`](R) reader structure"]
96impl crate::Readable for RNG_CFG_SPEC {}
97#[doc = "`write(|w| ..)` method takes [`rng_cfg::W`](W) writer structure"]
98impl crate::Writable for RNG_CFG_SPEC {
99    type Safety = crate::Unsafe;
100    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
101    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102}
103#[doc = "`reset()` method sets RNG_CFG to value 0x03"]
104impl crate::Resettable for RNG_CFG_SPEC {
105    const RESET_VALUE: u32 = 0x03;
106}
esp32p4/lp_sys/rng_cfg.rs

esp32p4/lp_sys/
rng_cfg.rs
