esp32p4/assist_debug/
core_1_intr_clr.rs

1#[doc = "Register `CORE_1_INTR_CLR` writer"]
2pub type W = crate::W<CORE_1_INTR_CLR_SPEC>;
3#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_CLR` writer - Core1 dram0 area0 read monitor interrupt clr"]
4pub type CORE_1_AREA_DRAM0_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_CLR` writer - Core1 dram0 area0 write monitor interrupt clr"]
6pub type CORE_1_AREA_DRAM0_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_CLR` writer - Core1 dram0 area1 read monitor interrupt clr"]
8pub type CORE_1_AREA_DRAM0_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_CLR` writer - Core1 dram0 area1 write monitor interrupt clr"]
10pub type CORE_1_AREA_DRAM0_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `CORE_1_AREA_PIF_0_RD_CLR` writer - Core1 PIF area0 read monitor interrupt clr"]
12pub type CORE_1_AREA_PIF_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CORE_1_AREA_PIF_0_WR_CLR` writer - Core1 PIF area0 write monitor interrupt clr"]
14pub type CORE_1_AREA_PIF_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `CORE_1_AREA_PIF_1_RD_CLR` writer - Core1 PIF area1 read monitor interrupt clr"]
16pub type CORE_1_AREA_PIF_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CORE_1_AREA_PIF_1_WR_CLR` writer - Core1 PIF area1 write monitor interrupt clr"]
18pub type CORE_1_AREA_PIF_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `CORE_1_SP_SPILL_MIN_CLR` writer - Core1 stackpoint underflow monitor interrupt clr"]
20pub type CORE_1_SP_SPILL_MIN_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CORE_1_SP_SPILL_MAX_CLR` writer - Core1 stackpoint overflow monitor interrupt clr"]
22pub type CORE_1_SP_SPILL_MAX_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_CLR` writer - IBUS busy monitor interrupt clr"]
24pub type CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_CLR` writer - DBUS busy monitor interrupt clr"]
26pub type CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for crate::generic::Reg<CORE_1_INTR_CLR_SPEC> {
29    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
30        write!(f, "(not readable)")
31    }
32}
33impl W {
34    #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt clr"]
35    #[inline(always)]
36    #[must_use]
37    pub fn core_1_area_dram0_0_rd_clr(
38        &mut self,
39    ) -> CORE_1_AREA_DRAM0_0_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
40        CORE_1_AREA_DRAM0_0_RD_CLR_W::new(self, 0)
41    }
42    #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt clr"]
43    #[inline(always)]
44    #[must_use]
45    pub fn core_1_area_dram0_0_wr_clr(
46        &mut self,
47    ) -> CORE_1_AREA_DRAM0_0_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
48        CORE_1_AREA_DRAM0_0_WR_CLR_W::new(self, 1)
49    }
50    #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt clr"]
51    #[inline(always)]
52    #[must_use]
53    pub fn core_1_area_dram0_1_rd_clr(
54        &mut self,
55    ) -> CORE_1_AREA_DRAM0_1_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
56        CORE_1_AREA_DRAM0_1_RD_CLR_W::new(self, 2)
57    }
58    #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt clr"]
59    #[inline(always)]
60    #[must_use]
61    pub fn core_1_area_dram0_1_wr_clr(
62        &mut self,
63    ) -> CORE_1_AREA_DRAM0_1_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
64        CORE_1_AREA_DRAM0_1_WR_CLR_W::new(self, 3)
65    }
66    #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt clr"]
67    #[inline(always)]
68    #[must_use]
69    pub fn core_1_area_pif_0_rd_clr(&mut self) -> CORE_1_AREA_PIF_0_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
70        CORE_1_AREA_PIF_0_RD_CLR_W::new(self, 4)
71    }
72    #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt clr"]
73    #[inline(always)]
74    #[must_use]
75    pub fn core_1_area_pif_0_wr_clr(&mut self) -> CORE_1_AREA_PIF_0_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
76        CORE_1_AREA_PIF_0_WR_CLR_W::new(self, 5)
77    }
78    #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt clr"]
79    #[inline(always)]
80    #[must_use]
81    pub fn core_1_area_pif_1_rd_clr(&mut self) -> CORE_1_AREA_PIF_1_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
82        CORE_1_AREA_PIF_1_RD_CLR_W::new(self, 6)
83    }
84    #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt clr"]
85    #[inline(always)]
86    #[must_use]
87    pub fn core_1_area_pif_1_wr_clr(&mut self) -> CORE_1_AREA_PIF_1_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
88        CORE_1_AREA_PIF_1_WR_CLR_W::new(self, 7)
89    }
90    #[doc = "Bit 8 - Core1 stackpoint underflow monitor interrupt clr"]
91    #[inline(always)]
92    #[must_use]
93    pub fn core_1_sp_spill_min_clr(&mut self) -> CORE_1_SP_SPILL_MIN_CLR_W<CORE_1_INTR_CLR_SPEC> {
94        CORE_1_SP_SPILL_MIN_CLR_W::new(self, 8)
95    }
96    #[doc = "Bit 9 - Core1 stackpoint overflow monitor interrupt clr"]
97    #[inline(always)]
98    #[must_use]
99    pub fn core_1_sp_spill_max_clr(&mut self) -> CORE_1_SP_SPILL_MAX_CLR_W<CORE_1_INTR_CLR_SPEC> {
100        CORE_1_SP_SPILL_MAX_CLR_W::new(self, 9)
101    }
102    #[doc = "Bit 10 - IBUS busy monitor interrupt clr"]
103    #[inline(always)]
104    #[must_use]
105    pub fn core_1_iram0_exception_monitor_clr(
106        &mut self,
107    ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_W<CORE_1_INTR_CLR_SPEC> {
108        CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 10)
109    }
110    #[doc = "Bit 11 - DBUS busy monitor interrupt clr"]
111    #[inline(always)]
112    #[must_use]
113    pub fn core_1_dram0_exception_monitor_clr(
114        &mut self,
115    ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_W<CORE_1_INTR_CLR_SPEC> {
116        CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 11)
117    }
118}
119#[doc = "core1 monitor interrupt clr register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`core_1_intr_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
120pub struct CORE_1_INTR_CLR_SPEC;
121impl crate::RegisterSpec for CORE_1_INTR_CLR_SPEC {
122    type Ux = u32;
123}
124#[doc = "`write(|w| ..)` method takes [`core_1_intr_clr::W`](W) writer structure"]
125impl crate::Writable for CORE_1_INTR_CLR_SPEC {
126    type Safety = crate::Unsafe;
127    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
128    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
129}
130#[doc = "`reset()` method sets CORE_1_INTR_CLR to value 0"]
131impl crate::Resettable for CORE_1_INTR_CLR_SPEC {
132    const RESET_VALUE: u32 = 0;
133}
esp32p4/assist_debug/core_1_intr_clr.rs

esp32p4/assist_debug/
core_1_intr_clr.rs
