1#[doc = "Register `DOUT_MODE` reader"]
2pub type R = crate::R<DOUT_MODE_SPEC>;
3#[doc = "Register `DOUT_MODE` writer"]
4pub type W = crate::W<DOUT_MODE_SPEC>;
5#[doc = "Field `DOUT0_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
6pub type DOUT0_MODE_R = crate::BitReader;
7#[doc = "Field `DOUT0_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
8pub type DOUT0_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DOUT1_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
10pub type DOUT1_MODE_R = crate::BitReader;
11#[doc = "Field `DOUT1_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
12pub type DOUT1_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DOUT2_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
14pub type DOUT2_MODE_R = crate::BitReader;
15#[doc = "Field `DOUT2_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
16pub type DOUT2_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DOUT3_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
18pub type DOUT3_MODE_R = crate::BitReader;
19#[doc = "Field `DOUT3_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
20pub type DOUT3_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DOUT4_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
22pub type DOUT4_MODE_R = crate::BitReader;
23#[doc = "Field `DOUT4_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
24pub type DOUT4_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DOUT5_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
26pub type DOUT5_MODE_R = crate::BitReader;
27#[doc = "Field `DOUT5_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
28pub type DOUT5_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DOUT6_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
30pub type DOUT6_MODE_R = crate::BitReader;
31#[doc = "Field `DOUT6_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
32pub type DOUT6_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DOUT7_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
34pub type DOUT7_MODE_R = crate::BitReader;
35#[doc = "Field `DOUT7_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
36pub type DOUT7_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DOUTS_MODE` reader - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
38pub type DOUTS_MODE_R = crate::BitReader;
39#[doc = "Field `DOUTS_MODE` writer - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
40pub type DOUTS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42 #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
43 #[inline(always)]
44 pub fn dout0_mode(&self) -> DOUT0_MODE_R {
45 DOUT0_MODE_R::new((self.bits & 1) != 0)
46 }
47 #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
48 #[inline(always)]
49 pub fn dout1_mode(&self) -> DOUT1_MODE_R {
50 DOUT1_MODE_R::new(((self.bits >> 1) & 1) != 0)
51 }
52 #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
53 #[inline(always)]
54 pub fn dout2_mode(&self) -> DOUT2_MODE_R {
55 DOUT2_MODE_R::new(((self.bits >> 2) & 1) != 0)
56 }
57 #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
58 #[inline(always)]
59 pub fn dout3_mode(&self) -> DOUT3_MODE_R {
60 DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0)
61 }
62 #[doc = "Bit 4 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
63 #[inline(always)]
64 pub fn dout4_mode(&self) -> DOUT4_MODE_R {
65 DOUT4_MODE_R::new(((self.bits >> 4) & 1) != 0)
66 }
67 #[doc = "Bit 5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
68 #[inline(always)]
69 pub fn dout5_mode(&self) -> DOUT5_MODE_R {
70 DOUT5_MODE_R::new(((self.bits >> 5) & 1) != 0)
71 }
72 #[doc = "Bit 6 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
73 #[inline(always)]
74 pub fn dout6_mode(&self) -> DOUT6_MODE_R {
75 DOUT6_MODE_R::new(((self.bits >> 6) & 1) != 0)
76 }
77 #[doc = "Bit 7 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
78 #[inline(always)]
79 pub fn dout7_mode(&self) -> DOUT7_MODE_R {
80 DOUT7_MODE_R::new(((self.bits >> 7) & 1) != 0)
81 }
82 #[doc = "Bit 8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
83 #[inline(always)]
84 pub fn douts_mode(&self) -> DOUTS_MODE_R {
85 DOUTS_MODE_R::new(((self.bits >> 8) & 1) != 0)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("DOUT_MODE")
92 .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
93 .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
94 .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
95 .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
96 .field("dout4_mode", &format_args!("{}", self.dout4_mode().bit()))
97 .field("dout5_mode", &format_args!("{}", self.dout5_mode().bit()))
98 .field("dout6_mode", &format_args!("{}", self.dout6_mode().bit()))
99 .field("dout7_mode", &format_args!("{}", self.dout7_mode().bit()))
100 .field("douts_mode", &format_args!("{}", self.douts_mode().bit()))
101 .finish()
102 }
103}
104#[cfg(feature = "impl-register-debug")]
105impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
106 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
107 core::fmt::Debug::fmt(&self.read(), f)
108 }
109}
110impl W {
111 #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
112 #[inline(always)]
113 #[must_use]
114 pub fn dout0_mode(&mut self) -> DOUT0_MODE_W<DOUT_MODE_SPEC> {
115 DOUT0_MODE_W::new(self, 0)
116 }
117 #[doc = "Bit 1 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
118 #[inline(always)]
119 #[must_use]
120 pub fn dout1_mode(&mut self) -> DOUT1_MODE_W<DOUT_MODE_SPEC> {
121 DOUT1_MODE_W::new(self, 1)
122 }
123 #[doc = "Bit 2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
124 #[inline(always)]
125 #[must_use]
126 pub fn dout2_mode(&mut self) -> DOUT2_MODE_W<DOUT_MODE_SPEC> {
127 DOUT2_MODE_W::new(self, 2)
128 }
129 #[doc = "Bit 3 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
130 #[inline(always)]
131 #[must_use]
132 pub fn dout3_mode(&mut self) -> DOUT3_MODE_W<DOUT_MODE_SPEC> {
133 DOUT3_MODE_W::new(self, 3)
134 }
135 #[doc = "Bit 4 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
136 #[inline(always)]
137 #[must_use]
138 pub fn dout4_mode(&mut self) -> DOUT4_MODE_W<DOUT_MODE_SPEC> {
139 DOUT4_MODE_W::new(self, 4)
140 }
141 #[doc = "Bit 5 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
142 #[inline(always)]
143 #[must_use]
144 pub fn dout5_mode(&mut self) -> DOUT5_MODE_W<DOUT_MODE_SPEC> {
145 DOUT5_MODE_W::new(self, 5)
146 }
147 #[doc = "Bit 6 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
148 #[inline(always)]
149 #[must_use]
150 pub fn dout6_mode(&mut self) -> DOUT6_MODE_W<DOUT_MODE_SPEC> {
151 DOUT6_MODE_W::new(self, 6)
152 }
153 #[doc = "Bit 7 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
154 #[inline(always)]
155 #[must_use]
156 pub fn dout7_mode(&mut self) -> DOUT7_MODE_W<DOUT_MODE_SPEC> {
157 DOUT7_MODE_W::new(self, 7)
158 }
159 #[doc = "Bit 8 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk"]
160 #[inline(always)]
161 #[must_use]
162 pub fn douts_mode(&mut self) -> DOUTS_MODE_W<DOUT_MODE_SPEC> {
163 DOUTS_MODE_W::new(self, 8)
164 }
165}
166#[doc = "MSPI flash output timing adjustment control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dout_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct DOUT_MODE_SPEC;
168impl crate::RegisterSpec for DOUT_MODE_SPEC {
169 type Ux = u32;
170}
171#[doc = "`read()` method returns [`dout_mode::R`](R) reader structure"]
172impl crate::Readable for DOUT_MODE_SPEC {}
173#[doc = "`write(|w| ..)` method takes [`dout_mode::W`](W) writer structure"]
174impl crate::Writable for DOUT_MODE_SPEC {
175 type Safety = crate::Unsafe;
176 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
177 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
178}
179#[doc = "`reset()` method sets DOUT_MODE to value 0"]
180impl crate::Resettable for DOUT_MODE_SPEC {
181 const RESET_VALUE: u32 = 0;
182}