esp32p4/cache/
l1_dbus1_acs_hit_cnt.rs

1#[doc = "Register `L1_DBUS1_ACS_HIT_CNT` reader"]
2pub type R = crate::R<L1_DBUS1_ACS_HIT_CNT_SPEC>;
3#[doc = "Field `L1_DBUS1_HIT_CNT` reader - The register records the number of hits when bus1 accesses L1-DCache."]
4pub type L1_DBUS1_HIT_CNT_R = crate::FieldReader<u32>;
5impl R {
6    #[doc = "Bits 0:31 - The register records the number of hits when bus1 accesses L1-DCache."]
7    #[inline(always)]
8    pub fn l1_dbus1_hit_cnt(&self) -> L1_DBUS1_HIT_CNT_R {
9        L1_DBUS1_HIT_CNT_R::new(self.bits)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("L1_DBUS1_ACS_HIT_CNT")
16            .field(
17                "l1_dbus1_hit_cnt",
18                &format_args!("{}", self.l1_dbus1_hit_cnt().bits()),
19            )
20            .finish()
21    }
22}
23#[cfg(feature = "impl-register-debug")]
24impl core::fmt::Debug for crate::generic::Reg<L1_DBUS1_ACS_HIT_CNT_SPEC> {
25    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
26        core::fmt::Debug::fmt(&self.read(), f)
27    }
28}
29#[doc = "L1-DCache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30pub struct L1_DBUS1_ACS_HIT_CNT_SPEC;
31impl crate::RegisterSpec for L1_DBUS1_ACS_HIT_CNT_SPEC {
32    type Ux = u32;
33}
34#[doc = "`read()` method returns [`l1_dbus1_acs_hit_cnt::R`](R) reader structure"]
35impl crate::Readable for L1_DBUS1_ACS_HIT_CNT_SPEC {}
36#[doc = "`reset()` method sets L1_DBUS1_ACS_HIT_CNT to value 0"]
37impl crate::Resettable for L1_DBUS1_ACS_HIT_CNT_SPEC {
38    const RESET_VALUE: u32 = 0;
39}
esp32p4/cache/l1_dbus1_acs_hit_cnt.rs

esp32p4/cache/
l1_dbus1_acs_hit_cnt.rs
