#[repr(C)]pub struct RegisterBlock { /* private fields */ }
Expand description
Register block
Implementations§
Source§impl RegisterBlock
impl RegisterBlock
Sourcepub const fn core_0_intr_ena(&self) -> &CORE_0_INTR_ENA
pub const fn core_0_intr_ena(&self) -> &CORE_0_INTR_ENA
0x00 - core0 monitor enable configuration register
Sourcepub const fn core_0_intr_raw(&self) -> &CORE_0_INTR_RAW
pub const fn core_0_intr_raw(&self) -> &CORE_0_INTR_RAW
0x04 - core0 monitor interrupt status register
Sourcepub const fn core_0_intr_rls(&self) -> &CORE_0_INTR_RLS
pub const fn core_0_intr_rls(&self) -> &CORE_0_INTR_RLS
0x08 - core0 monitor interrupt enable register
Sourcepub const fn core_0_intr_clr(&self) -> &CORE_0_INTR_CLR
pub const fn core_0_intr_clr(&self) -> &CORE_0_INTR_CLR
0x0c - core0 monitor interrupt clr register
Sourcepub const fn core_0_area_dram0_0_min(&self) -> &CORE_0_AREA_DRAM0_0_MIN
pub const fn core_0_area_dram0_0_min(&self) -> &CORE_0_AREA_DRAM0_0_MIN
0x10 - core0 dram0 region0 addr configuration register
Sourcepub const fn core_0_area_dram0_0_max(&self) -> &CORE_0_AREA_DRAM0_0_MAX
pub const fn core_0_area_dram0_0_max(&self) -> &CORE_0_AREA_DRAM0_0_MAX
0x14 - core0 dram0 region0 addr configuration register
Sourcepub const fn core_0_area_dram0_1_min(&self) -> &CORE_0_AREA_DRAM0_1_MIN
pub const fn core_0_area_dram0_1_min(&self) -> &CORE_0_AREA_DRAM0_1_MIN
0x18 - core0 dram0 region1 addr configuration register
Sourcepub const fn core_0_area_dram0_1_max(&self) -> &CORE_0_AREA_DRAM0_1_MAX
pub const fn core_0_area_dram0_1_max(&self) -> &CORE_0_AREA_DRAM0_1_MAX
0x1c - core0 dram0 region1 addr configuration register
Sourcepub const fn core_0_area_pif_0_min(&self) -> &CORE_0_AREA_PIF_0_MIN
pub const fn core_0_area_pif_0_min(&self) -> &CORE_0_AREA_PIF_0_MIN
0x20 - core0 PIF region0 addr configuration register
Sourcepub const fn core_0_area_pif_0_max(&self) -> &CORE_0_AREA_PIF_0_MAX
pub const fn core_0_area_pif_0_max(&self) -> &CORE_0_AREA_PIF_0_MAX
0x24 - core0 PIF region0 addr configuration register
Sourcepub const fn core_0_area_pif_1_min(&self) -> &CORE_0_AREA_PIF_1_MIN
pub const fn core_0_area_pif_1_min(&self) -> &CORE_0_AREA_PIF_1_MIN
0x28 - core0 PIF region1 addr configuration register
Sourcepub const fn core_0_area_pif_1_max(&self) -> &CORE_0_AREA_PIF_1_MAX
pub const fn core_0_area_pif_1_max(&self) -> &CORE_0_AREA_PIF_1_MAX
0x2c - core0 PIF region1 addr configuration register
Sourcepub const fn core_0_area_pc(&self) -> &CORE_0_AREA_PC
pub const fn core_0_area_pc(&self) -> &CORE_0_AREA_PC
0x30 - core0 area pc status register
Sourcepub const fn core_0_area_sp(&self) -> &CORE_0_AREA_SP
pub const fn core_0_area_sp(&self) -> &CORE_0_AREA_SP
0x34 - core0 area sp status register
Sourcepub const fn core_0_sp_min(&self) -> &CORE_0_SP_MIN
pub const fn core_0_sp_min(&self) -> &CORE_0_SP_MIN
0x38 - stack min value
Sourcepub const fn core_0_sp_max(&self) -> &CORE_0_SP_MAX
pub const fn core_0_sp_max(&self) -> &CORE_0_SP_MAX
0x3c - stack max value
Sourcepub const fn core_0_sp_pc(&self) -> &CORE_0_SP_PC
pub const fn core_0_sp_pc(&self) -> &CORE_0_SP_PC
0x40 - stack monitor pc status register
Sourcepub const fn core_0_rcd_en(&self) -> &CORE_0_RCD_EN
pub const fn core_0_rcd_en(&self) -> &CORE_0_RCD_EN
0x44 - record enable configuration register
Sourcepub const fn core_0_rcd_pdebugpc(&self) -> &CORE_0_RCD_PDEBUGPC
pub const fn core_0_rcd_pdebugpc(&self) -> &CORE_0_RCD_PDEBUGPC
0x48 - record status regsiter
Sourcepub const fn core_0_rcd_pdebugsp(&self) -> &CORE_0_RCD_PDEBUGSP
pub const fn core_0_rcd_pdebugsp(&self) -> &CORE_0_RCD_PDEBUGSP
0x4c - record status regsiter
Sourcepub const fn core_0_iram0_exception_monitor_0(
&self,
) -> &CORE_0_IRAM0_EXCEPTION_MONITOR_0
pub const fn core_0_iram0_exception_monitor_0( &self, ) -> &CORE_0_IRAM0_EXCEPTION_MONITOR_0
0x50 - exception monitor status register0
Sourcepub const fn core_0_iram0_exception_monitor_1(
&self,
) -> &CORE_0_IRAM0_EXCEPTION_MONITOR_1
pub const fn core_0_iram0_exception_monitor_1( &self, ) -> &CORE_0_IRAM0_EXCEPTION_MONITOR_1
0x54 - exception monitor status register1
Sourcepub const fn core_0_dram0_exception_monitor_0(
&self,
) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_0
pub const fn core_0_dram0_exception_monitor_0( &self, ) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_0
0x58 - exception monitor status register2
Sourcepub const fn core_0_dram0_exception_monitor_1(
&self,
) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_1
pub const fn core_0_dram0_exception_monitor_1( &self, ) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_1
0x5c - exception monitor status register3
Sourcepub const fn core_0_dram0_exception_monitor_2(
&self,
) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_2
pub const fn core_0_dram0_exception_monitor_2( &self, ) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_2
0x60 - exception monitor status register4
Sourcepub const fn core_0_dram0_exception_monitor_3(
&self,
) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_3
pub const fn core_0_dram0_exception_monitor_3( &self, ) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_3
0x64 - exception monitor status register5
Sourcepub const fn core_0_dram0_exception_monitor_4(
&self,
) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_4
pub const fn core_0_dram0_exception_monitor_4( &self, ) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_4
0x68 - exception monitor status register6
Sourcepub const fn core_0_dram0_exception_monitor_5(
&self,
) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_5
pub const fn core_0_dram0_exception_monitor_5( &self, ) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_5
0x6c - exception monitor status register7
Sourcepub const fn core_0_lastpc_before_exception(
&self,
) -> &CORE_0_LASTPC_BEFORE_EXCEPTION
pub const fn core_0_lastpc_before_exception( &self, ) -> &CORE_0_LASTPC_BEFORE_EXCEPTION
0x70 - cpu status register
Sourcepub const fn core_0_debug_mode(&self) -> &CORE_0_DEBUG_MODE
pub const fn core_0_debug_mode(&self) -> &CORE_0_DEBUG_MODE
0x74 - cpu status register
Sourcepub const fn core_1_intr_ena(&self) -> &CORE_1_INTR_ENA
pub const fn core_1_intr_ena(&self) -> &CORE_1_INTR_ENA
0x80 - core1 monitor enable configuration register
Sourcepub const fn core_1_intr_raw(&self) -> &CORE_1_INTR_RAW
pub const fn core_1_intr_raw(&self) -> &CORE_1_INTR_RAW
0x84 - core1 monitor interrupt status register
Sourcepub const fn core_1_intr_rls(&self) -> &CORE_1_INTR_RLS
pub const fn core_1_intr_rls(&self) -> &CORE_1_INTR_RLS
0x88 - core1 monitor interrupt enable register
Sourcepub const fn core_1_intr_clr(&self) -> &CORE_1_INTR_CLR
pub const fn core_1_intr_clr(&self) -> &CORE_1_INTR_CLR
0x8c - core1 monitor interrupt clr register
Sourcepub const fn core_1_area_dram0_0_min(&self) -> &CORE_1_AREA_DRAM0_0_MIN
pub const fn core_1_area_dram0_0_min(&self) -> &CORE_1_AREA_DRAM0_0_MIN
0x90 - core1 dram0 region0 addr configuration register
Sourcepub const fn core_1_area_dram0_0_max(&self) -> &CORE_1_AREA_DRAM0_0_MAX
pub const fn core_1_area_dram0_0_max(&self) -> &CORE_1_AREA_DRAM0_0_MAX
0x94 - core1 dram0 region0 addr configuration register
Sourcepub const fn core_1_area_dram0_1_min(&self) -> &CORE_1_AREA_DRAM0_1_MIN
pub const fn core_1_area_dram0_1_min(&self) -> &CORE_1_AREA_DRAM0_1_MIN
0x98 - core1 dram0 region1 addr configuration register
Sourcepub const fn core_1_area_dram0_1_max(&self) -> &CORE_1_AREA_DRAM0_1_MAX
pub const fn core_1_area_dram0_1_max(&self) -> &CORE_1_AREA_DRAM0_1_MAX
0x9c - core1 dram0 region1 addr configuration register
Sourcepub const fn core_1_area_pif_0_min(&self) -> &CORE_1_AREA_PIF_0_MIN
pub const fn core_1_area_pif_0_min(&self) -> &CORE_1_AREA_PIF_0_MIN
0xa0 - core1 PIF region0 addr configuration register
Sourcepub const fn core_1_area_pif_0_max(&self) -> &CORE_1_AREA_PIF_0_MAX
pub const fn core_1_area_pif_0_max(&self) -> &CORE_1_AREA_PIF_0_MAX
0xa4 - core1 PIF region0 addr configuration register
Sourcepub const fn core_1_area_pif_1_min(&self) -> &CORE_1_AREA_PIF_1_MIN
pub const fn core_1_area_pif_1_min(&self) -> &CORE_1_AREA_PIF_1_MIN
0xa8 - core1 PIF region1 addr configuration register
Sourcepub const fn core_1_area_pif_1_max(&self) -> &CORE_1_AREA_PIF_1_MAX
pub const fn core_1_area_pif_1_max(&self) -> &CORE_1_AREA_PIF_1_MAX
0xac - core1 PIF region1 addr configuration register
Sourcepub const fn core_1_area_pc(&self) -> &CORE_1_AREA_PC
pub const fn core_1_area_pc(&self) -> &CORE_1_AREA_PC
0xb0 - core1 area pc status register
Sourcepub const fn core_1_area_sp(&self) -> &CORE_1_AREA_SP
pub const fn core_1_area_sp(&self) -> &CORE_1_AREA_SP
0xb4 - core1 area sp status register
Sourcepub const fn core_1_sp_min(&self) -> &CORE_1_SP_MIN
pub const fn core_1_sp_min(&self) -> &CORE_1_SP_MIN
0xb8 - stack min value
Sourcepub const fn core_1_sp_max(&self) -> &CORE_1_SP_MAX
pub const fn core_1_sp_max(&self) -> &CORE_1_SP_MAX
0xbc - stack max value
Sourcepub const fn core_1_sp_pc(&self) -> &CORE_1_SP_PC
pub const fn core_1_sp_pc(&self) -> &CORE_1_SP_PC
0xc0 - stack monitor pc status register
Sourcepub const fn core_1_rcd_en(&self) -> &CORE_1_RCD_EN
pub const fn core_1_rcd_en(&self) -> &CORE_1_RCD_EN
0xc4 - record enable configuration register
Sourcepub const fn core_1_rcd_pdebugpc(&self) -> &CORE_1_RCD_PDEBUGPC
pub const fn core_1_rcd_pdebugpc(&self) -> &CORE_1_RCD_PDEBUGPC
0xc8 - record status regsiter
Sourcepub const fn core_1_rcd_pdebugsp(&self) -> &CORE_1_RCD_PDEBUGSP
pub const fn core_1_rcd_pdebugsp(&self) -> &CORE_1_RCD_PDEBUGSP
0xcc - record status regsiter
Sourcepub const fn core_1_iram0_exception_monitor_0(
&self,
) -> &CORE_1_IRAM0_EXCEPTION_MONITOR_0
pub const fn core_1_iram0_exception_monitor_0( &self, ) -> &CORE_1_IRAM0_EXCEPTION_MONITOR_0
0xd0 - exception monitor status register0
Sourcepub const fn core_1_iram0_exception_monitor_1(
&self,
) -> &CORE_1_IRAM0_EXCEPTION_MONITOR_1
pub const fn core_1_iram0_exception_monitor_1( &self, ) -> &CORE_1_IRAM0_EXCEPTION_MONITOR_1
0xd4 - exception monitor status register1
Sourcepub const fn core_1_dram0_exception_monitor_0(
&self,
) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_0
pub const fn core_1_dram0_exception_monitor_0( &self, ) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_0
0xd8 - exception monitor status register2
Sourcepub const fn core_1_dram0_exception_monitor_1(
&self,
) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_1
pub const fn core_1_dram0_exception_monitor_1( &self, ) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_1
0xdc - exception monitor status register3
Sourcepub const fn core_1_dram0_exception_monitor_2(
&self,
) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_2
pub const fn core_1_dram0_exception_monitor_2( &self, ) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_2
0xe0 - exception monitor status register4
Sourcepub const fn core_1_dram0_exception_monitor_3(
&self,
) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_3
pub const fn core_1_dram0_exception_monitor_3( &self, ) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_3
0xe4 - exception monitor status register5
Sourcepub const fn core_1_dram0_exception_monitor_4(
&self,
) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_4
pub const fn core_1_dram0_exception_monitor_4( &self, ) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_4
0xe8 - exception monitor status register6
Sourcepub const fn core_1_dram0_exception_monitor_5(
&self,
) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_5
pub const fn core_1_dram0_exception_monitor_5( &self, ) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_5
0xec - exception monitor status register7
Sourcepub const fn core_1_lastpc_before_exception(
&self,
) -> &CORE_1_LASTPC_BEFORE_EXCEPTION
pub const fn core_1_lastpc_before_exception( &self, ) -> &CORE_1_LASTPC_BEFORE_EXCEPTION
0xf0 - cpu status register
Sourcepub const fn core_1_debug_mode(&self) -> &CORE_1_DEBUG_MODE
pub const fn core_1_debug_mode(&self) -> &CORE_1_DEBUG_MODE
0xf4 - cpu status register
Sourcepub const fn core_x_iram0_dram0_exception_monitor_0(
&self,
) -> &CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0
pub const fn core_x_iram0_dram0_exception_monitor_0( &self, ) -> &CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0
0x100 - exception monitor status register6
Sourcepub const fn core_x_iram0_dram0_exception_monitor_1(
&self,
) -> &CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1
pub const fn core_x_iram0_dram0_exception_monitor_1( &self, ) -> &CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1
0x104 - exception monitor status register7
Sourcepub const fn clock_gate(&self) -> &CLOCK_GATE
pub const fn clock_gate(&self) -> &CLOCK_GATE
0x108 - clock register