esp32p4/
rmt.rs

1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    tx_chdata: [TX_CHDATA; 4],
6    rx_chdata: [RX_CHDATA; 4],
7    tx_chconf0: [TX_CHCONF0; 4],
8    rx_chconf0: (),
9    _reserved4: [u8; 0x04],
10    rx_chconf1: (),
11    _reserved5: [u8; 0x1c],
12    tx_chstatus: [TX_CHSTATUS; 4],
13    rx_chstatus: [RX_CHSTATUS; 4],
14    int_raw: INT_RAW,
15    int_st: INT_ST,
16    int_ena: INT_ENA,
17    int_clr: INT_CLR,
18    chcarrier_duty: [CHCARRIER_DUTY; 4],
19    ch_rx_carrier_rm: [CH_RX_CARRIER_RM; 4],
20    ch_tx_lim: [CH_TX_LIM; 4],
21    ch_rx_lim: [CH_RX_LIM; 4],
22    sys_conf: SYS_CONF,
23    tx_sim: TX_SIM,
24    ref_cnt_rst: REF_CNT_RST,
25    date: DATE,
26}
27impl RegisterBlock {
28    #[doc = "0x00..0x10 - The read and write data register for CHANNEL%s by apb fifo access."]
29    #[inline(always)]
30    pub const fn tx_chdata(&self, n: usize) -> &TX_CHDATA {
31        &self.tx_chdata[n]
32    }
33    #[doc = "Iterator for array of:"]
34    #[doc = "0x00..0x10 - The read and write data register for CHANNEL%s by apb fifo access."]
35    #[inline(always)]
36    pub fn tx_chdata_iter(&self) -> impl Iterator<Item = &TX_CHDATA> {
37        self.tx_chdata.iter()
38    }
39    #[doc = "0x00 - The read and write data register for CHANNEL0 by apb fifo access."]
40    #[inline(always)]
41    pub const fn tx_ch0data(&self) -> &TX_CHDATA {
42        self.tx_chdata(0)
43    }
44    #[doc = "0x04 - The read and write data register for CHANNEL1 by apb fifo access."]
45    #[inline(always)]
46    pub const fn tx_ch1data(&self) -> &TX_CHDATA {
47        self.tx_chdata(1)
48    }
49    #[doc = "0x08 - The read and write data register for CHANNEL2 by apb fifo access."]
50    #[inline(always)]
51    pub const fn tx_ch2data(&self) -> &TX_CHDATA {
52        self.tx_chdata(2)
53    }
54    #[doc = "0x0c - The read and write data register for CHANNEL3 by apb fifo access."]
55    #[inline(always)]
56    pub const fn tx_ch3data(&self) -> &TX_CHDATA {
57        self.tx_chdata(3)
58    }
59    #[doc = "0x10..0x20 - The read and write data register for CHANNEL$n by apb fifo access."]
60    #[inline(always)]
61    pub const fn rx_chdata(&self, n: usize) -> &RX_CHDATA {
62        &self.rx_chdata[n]
63    }
64    #[doc = "Iterator for array of:"]
65    #[doc = "0x10..0x20 - The read and write data register for CHANNEL$n by apb fifo access."]
66    #[inline(always)]
67    pub fn rx_chdata_iter(&self) -> impl Iterator<Item = &RX_CHDATA> {
68        self.rx_chdata.iter()
69    }
70    #[doc = "0x10 - The read and write data register for CHANNEL$n by apb fifo access."]
71    #[inline(always)]
72    pub const fn rx_ch0data(&self) -> &RX_CHDATA {
73        self.rx_chdata(0)
74    }
75    #[doc = "0x14 - The read and write data register for CHANNEL$n by apb fifo access."]
76    #[inline(always)]
77    pub const fn rx_ch1data(&self) -> &RX_CHDATA {
78        self.rx_chdata(1)
79    }
80    #[doc = "0x18 - The read and write data register for CHANNEL$n by apb fifo access."]
81    #[inline(always)]
82    pub const fn rx_ch2data(&self) -> &RX_CHDATA {
83        self.rx_chdata(2)
84    }
85    #[doc = "0x1c - The read and write data register for CHANNEL$n by apb fifo access."]
86    #[inline(always)]
87    pub const fn rx_ch3data(&self) -> &RX_CHDATA {
88        self.rx_chdata(3)
89    }
90    #[doc = "0x20..0x30 - Channel %s configure register 0"]
91    #[inline(always)]
92    pub const fn tx_chconf0(&self, n: usize) -> &TX_CHCONF0 {
93        &self.tx_chconf0[n]
94    }
95    #[doc = "Iterator for array of:"]
96    #[doc = "0x20..0x30 - Channel %s configure register 0"]
97    #[inline(always)]
98    pub fn tx_chconf0_iter(&self) -> impl Iterator<Item = &TX_CHCONF0> {
99        self.tx_chconf0.iter()
100    }
101    #[doc = "0x20 - Channel 0 configure register 0"]
102    #[inline(always)]
103    pub const fn tx_ch0conf0(&self) -> &TX_CHCONF0 {
104        self.tx_chconf0(0)
105    }
106    #[doc = "0x24 - Channel 1 configure register 0"]
107    #[inline(always)]
108    pub const fn tx_ch1conf0(&self) -> &TX_CHCONF0 {
109        self.tx_chconf0(1)
110    }
111    #[doc = "0x28 - Channel 2 configure register 0"]
112    #[inline(always)]
113    pub const fn tx_ch2conf0(&self) -> &TX_CHCONF0 {
114        self.tx_chconf0(2)
115    }
116    #[doc = "0x2c - Channel 3 configure register 0"]
117    #[inline(always)]
118    pub const fn tx_ch3conf0(&self) -> &TX_CHCONF0 {
119        self.tx_chconf0(3)
120    }
121    #[doc = "0x30..0x40 - Channel %s configure register 0"]
122    #[inline(always)]
123    pub const fn rx_chconf0(&self, n: usize) -> &RX_CHCONF0 {
124        #[allow(clippy::no_effect)]
125        [(); 4][n];
126        unsafe { &*(self as *const Self).cast::<u8>().add(48).add(8 * n).cast() }
127    }
128    #[doc = "Iterator for array of:"]
129    #[doc = "0x30..0x40 - Channel %s configure register 0"]
130    #[inline(always)]
131    pub fn rx_chconf0_iter(&self) -> impl Iterator<Item = &RX_CHCONF0> {
132        (0..4)
133            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(48).add(8 * n).cast() })
134    }
135    #[doc = "0x30 - Channel 0 configure register 0"]
136    #[inline(always)]
137    pub const fn rx_ch0conf0(&self) -> &RX_CHCONF0 {
138        self.rx_chconf0(0)
139    }
140    #[doc = "0x38 - Channel 1 configure register 0"]
141    #[inline(always)]
142    pub const fn rx_ch1conf0(&self) -> &RX_CHCONF0 {
143        self.rx_chconf0(1)
144    }
145    #[doc = "0x40 - Channel 2 configure register 0"]
146    #[inline(always)]
147    pub const fn rx_ch2conf0(&self) -> &RX_CHCONF0 {
148        self.rx_chconf0(2)
149    }
150    #[doc = "0x48 - Channel 3 configure register 0"]
151    #[inline(always)]
152    pub const fn rx_ch3conf0(&self) -> &RX_CHCONF0 {
153        self.rx_chconf0(3)
154    }
155    #[doc = "0x34..0x44 - Channel %s configure register 1"]
156    #[inline(always)]
157    pub const fn rx_chconf1(&self, n: usize) -> &RX_CHCONF1 {
158        #[allow(clippy::no_effect)]
159        [(); 4][n];
160        unsafe { &*(self as *const Self).cast::<u8>().add(52).add(8 * n).cast() }
161    }
162    #[doc = "Iterator for array of:"]
163    #[doc = "0x34..0x44 - Channel %s configure register 1"]
164    #[inline(always)]
165    pub fn rx_chconf1_iter(&self) -> impl Iterator<Item = &RX_CHCONF1> {
166        (0..4)
167            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(52).add(8 * n).cast() })
168    }
169    #[doc = "0x34 - Channel 0 configure register 1"]
170    #[inline(always)]
171    pub const fn rx_ch0conf1(&self) -> &RX_CHCONF1 {
172        self.rx_chconf1(0)
173    }
174    #[doc = "0x3c - Channel 1 configure register 1"]
175    #[inline(always)]
176    pub const fn rx_ch1conf1(&self) -> &RX_CHCONF1 {
177        self.rx_chconf1(1)
178    }
179    #[doc = "0x44 - Channel 2 configure register 1"]
180    #[inline(always)]
181    pub const fn rx_ch2conf1(&self) -> &RX_CHCONF1 {
182        self.rx_chconf1(2)
183    }
184    #[doc = "0x4c - Channel 3 configure register 1"]
185    #[inline(always)]
186    pub const fn rx_ch3conf1(&self) -> &RX_CHCONF1 {
187        self.rx_chconf1(3)
188    }
189    #[doc = "0x50..0x60 - Channel %s status register"]
190    #[inline(always)]
191    pub const fn tx_chstatus(&self, n: usize) -> &TX_CHSTATUS {
192        &self.tx_chstatus[n]
193    }
194    #[doc = "Iterator for array of:"]
195    #[doc = "0x50..0x60 - Channel %s status register"]
196    #[inline(always)]
197    pub fn tx_chstatus_iter(&self) -> impl Iterator<Item = &TX_CHSTATUS> {
198        self.tx_chstatus.iter()
199    }
200    #[doc = "0x50 - Channel 0 status register"]
201    #[inline(always)]
202    pub const fn tx_ch0status(&self) -> &TX_CHSTATUS {
203        self.tx_chstatus(0)
204    }
205    #[doc = "0x54 - Channel 1 status register"]
206    #[inline(always)]
207    pub const fn tx_ch1status(&self) -> &TX_CHSTATUS {
208        self.tx_chstatus(1)
209    }
210    #[doc = "0x58 - Channel 2 status register"]
211    #[inline(always)]
212    pub const fn tx_ch2status(&self) -> &TX_CHSTATUS {
213        self.tx_chstatus(2)
214    }
215    #[doc = "0x5c - Channel 3 status register"]
216    #[inline(always)]
217    pub const fn tx_ch3status(&self) -> &TX_CHSTATUS {
218        self.tx_chstatus(3)
219    }
220    #[doc = "0x60..0x70 - Channel %s status register"]
221    #[inline(always)]
222    pub const fn rx_chstatus(&self, n: usize) -> &RX_CHSTATUS {
223        &self.rx_chstatus[n]
224    }
225    #[doc = "Iterator for array of:"]
226    #[doc = "0x60..0x70 - Channel %s status register"]
227    #[inline(always)]
228    pub fn rx_chstatus_iter(&self) -> impl Iterator<Item = &RX_CHSTATUS> {
229        self.rx_chstatus.iter()
230    }
231    #[doc = "0x60 - Channel 0 status register"]
232    #[inline(always)]
233    pub const fn rx_ch0status(&self) -> &RX_CHSTATUS {
234        self.rx_chstatus(0)
235    }
236    #[doc = "0x64 - Channel 1 status register"]
237    #[inline(always)]
238    pub const fn rx_ch1status(&self) -> &RX_CHSTATUS {
239        self.rx_chstatus(1)
240    }
241    #[doc = "0x68 - Channel 2 status register"]
242    #[inline(always)]
243    pub const fn rx_ch2status(&self) -> &RX_CHSTATUS {
244        self.rx_chstatus(2)
245    }
246    #[doc = "0x6c - Channel 3 status register"]
247    #[inline(always)]
248    pub const fn rx_ch3status(&self) -> &RX_CHSTATUS {
249        self.rx_chstatus(3)
250    }
251    #[doc = "0x70 - Raw interrupt status"]
252    #[inline(always)]
253    pub const fn int_raw(&self) -> &INT_RAW {
254        &self.int_raw
255    }
256    #[doc = "0x74 - Masked interrupt status"]
257    #[inline(always)]
258    pub const fn int_st(&self) -> &INT_ST {
259        &self.int_st
260    }
261    #[doc = "0x78 - Interrupt enable bits"]
262    #[inline(always)]
263    pub const fn int_ena(&self) -> &INT_ENA {
264        &self.int_ena
265    }
266    #[doc = "0x7c - Interrupt clear bits"]
267    #[inline(always)]
268    pub const fn int_clr(&self) -> &INT_CLR {
269        &self.int_clr
270    }
271    #[doc = "0x80..0x90 - Channel %s duty cycle configuration register"]
272    #[inline(always)]
273    pub const fn chcarrier_duty(&self, n: usize) -> &CHCARRIER_DUTY {
274        &self.chcarrier_duty[n]
275    }
276    #[doc = "Iterator for array of:"]
277    #[doc = "0x80..0x90 - Channel %s duty cycle configuration register"]
278    #[inline(always)]
279    pub fn chcarrier_duty_iter(&self) -> impl Iterator<Item = &CHCARRIER_DUTY> {
280        self.chcarrier_duty.iter()
281    }
282    #[doc = "0x80 - Channel 0 duty cycle configuration register"]
283    #[inline(always)]
284    pub const fn ch0carrier_duty(&self) -> &CHCARRIER_DUTY {
285        self.chcarrier_duty(0)
286    }
287    #[doc = "0x84 - Channel 1 duty cycle configuration register"]
288    #[inline(always)]
289    pub const fn ch1carrier_duty(&self) -> &CHCARRIER_DUTY {
290        self.chcarrier_duty(1)
291    }
292    #[doc = "0x88 - Channel 2 duty cycle configuration register"]
293    #[inline(always)]
294    pub const fn ch2carrier_duty(&self) -> &CHCARRIER_DUTY {
295        self.chcarrier_duty(2)
296    }
297    #[doc = "0x8c - Channel 3 duty cycle configuration register"]
298    #[inline(always)]
299    pub const fn ch3carrier_duty(&self) -> &CHCARRIER_DUTY {
300        self.chcarrier_duty(3)
301    }
302    #[doc = "0x90..0xa0 - Channel %s carrier remove register"]
303    #[inline(always)]
304    pub const fn ch_rx_carrier_rm(&self, n: usize) -> &CH_RX_CARRIER_RM {
305        &self.ch_rx_carrier_rm[n]
306    }
307    #[doc = "Iterator for array of:"]
308    #[doc = "0x90..0xa0 - Channel %s carrier remove register"]
309    #[inline(always)]
310    pub fn ch_rx_carrier_rm_iter(&self) -> impl Iterator<Item = &CH_RX_CARRIER_RM> {
311        self.ch_rx_carrier_rm.iter()
312    }
313    #[doc = "0x90 - Channel 0 carrier remove register"]
314    #[inline(always)]
315    pub const fn ch0_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM {
316        self.ch_rx_carrier_rm(0)
317    }
318    #[doc = "0x94 - Channel 1 carrier remove register"]
319    #[inline(always)]
320    pub const fn ch1_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM {
321        self.ch_rx_carrier_rm(1)
322    }
323    #[doc = "0x98 - Channel 2 carrier remove register"]
324    #[inline(always)]
325    pub const fn ch2_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM {
326        self.ch_rx_carrier_rm(2)
327    }
328    #[doc = "0x9c - Channel 3 carrier remove register"]
329    #[inline(always)]
330    pub const fn ch3_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM {
331        self.ch_rx_carrier_rm(3)
332    }
333    #[doc = "0xa0..0xb0 - Channel %s Tx event configuration register"]
334    #[inline(always)]
335    pub const fn ch_tx_lim(&self, n: usize) -> &CH_TX_LIM {
336        &self.ch_tx_lim[n]
337    }
338    #[doc = "Iterator for array of:"]
339    #[doc = "0xa0..0xb0 - Channel %s Tx event configuration register"]
340    #[inline(always)]
341    pub fn ch_tx_lim_iter(&self) -> impl Iterator<Item = &CH_TX_LIM> {
342        self.ch_tx_lim.iter()
343    }
344    #[doc = "0xa0 - Channel 0 Tx event configuration register"]
345    #[inline(always)]
346    pub const fn ch0_tx_lim(&self) -> &CH_TX_LIM {
347        self.ch_tx_lim(0)
348    }
349    #[doc = "0xa4 - Channel 1 Tx event configuration register"]
350    #[inline(always)]
351    pub const fn ch1_tx_lim(&self) -> &CH_TX_LIM {
352        self.ch_tx_lim(1)
353    }
354    #[doc = "0xa8 - Channel 2 Tx event configuration register"]
355    #[inline(always)]
356    pub const fn ch2_tx_lim(&self) -> &CH_TX_LIM {
357        self.ch_tx_lim(2)
358    }
359    #[doc = "0xac - Channel 3 Tx event configuration register"]
360    #[inline(always)]
361    pub const fn ch3_tx_lim(&self) -> &CH_TX_LIM {
362        self.ch_tx_lim(3)
363    }
364    #[doc = "0xb0..0xc0 - Channel %s Rx event configuration register"]
365    #[inline(always)]
366    pub const fn ch_rx_lim(&self, n: usize) -> &CH_RX_LIM {
367        &self.ch_rx_lim[n]
368    }
369    #[doc = "Iterator for array of:"]
370    #[doc = "0xb0..0xc0 - Channel %s Rx event configuration register"]
371    #[inline(always)]
372    pub fn ch_rx_lim_iter(&self) -> impl Iterator<Item = &CH_RX_LIM> {
373        self.ch_rx_lim.iter()
374    }
375    #[doc = "0xb0 - Channel 0 Rx event configuration register"]
376    #[inline(always)]
377    pub const fn ch0_rx_lim(&self) -> &CH_RX_LIM {
378        self.ch_rx_lim(0)
379    }
380    #[doc = "0xb4 - Channel 1 Rx event configuration register"]
381    #[inline(always)]
382    pub const fn ch1_rx_lim(&self) -> &CH_RX_LIM {
383        self.ch_rx_lim(1)
384    }
385    #[doc = "0xb8 - Channel 2 Rx event configuration register"]
386    #[inline(always)]
387    pub const fn ch2_rx_lim(&self) -> &CH_RX_LIM {
388        self.ch_rx_lim(2)
389    }
390    #[doc = "0xbc - Channel 3 Rx event configuration register"]
391    #[inline(always)]
392    pub const fn ch3_rx_lim(&self) -> &CH_RX_LIM {
393        self.ch_rx_lim(3)
394    }
395    #[doc = "0xc0 - RMT apb configuration register"]
396    #[inline(always)]
397    pub const fn sys_conf(&self) -> &SYS_CONF {
398        &self.sys_conf
399    }
400    #[doc = "0xc4 - RMT TX synchronous register"]
401    #[inline(always)]
402    pub const fn tx_sim(&self) -> &TX_SIM {
403        &self.tx_sim
404    }
405    #[doc = "0xc8 - RMT clock divider reset register"]
406    #[inline(always)]
407    pub const fn ref_cnt_rst(&self) -> &REF_CNT_RST {
408        &self.ref_cnt_rst
409    }
410    #[doc = "0xcc - RMT version register"]
411    #[inline(always)]
412    pub const fn date(&self) -> &DATE {
413        &self.date
414    }
415}
416#[doc = "TX_CHDATA (r) register accessor: The read and write data register for CHANNEL%s by apb fifo access.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chdata::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_chdata`] module"]
417pub type TX_CHDATA = crate::Reg<tx_chdata::TX_CHDATA_SPEC>;
418#[doc = "The read and write data register for CHANNEL%s by apb fifo access."]
419pub mod tx_chdata;
420#[doc = "RX_CHDATA (r) register accessor: The read and write data register for CHANNEL$n by apb fifo access.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chdata::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_chdata`] module"]
421pub type RX_CHDATA = crate::Reg<rx_chdata::RX_CHDATA_SPEC>;
422#[doc = "The read and write data register for CHANNEL$n by apb fifo access."]
423pub mod rx_chdata;
424#[doc = "TX_CHCONF0 (rw) register accessor: Channel %s configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chconf0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_chconf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_chconf0`] module"]
425pub type TX_CHCONF0 = crate::Reg<tx_chconf0::TX_CHCONF0_SPEC>;
426#[doc = "Channel %s configure register 0"]
427pub mod tx_chconf0;
428#[doc = "RX_CHCONF0 (rw) register accessor: Channel %s configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chconf0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_chconf0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_chconf0`] module"]
429pub type RX_CHCONF0 = crate::Reg<rx_chconf0::RX_CHCONF0_SPEC>;
430#[doc = "Channel %s configure register 0"]
431pub mod rx_chconf0;
432#[doc = "RX_CHCONF1 (rw) register accessor: Channel %s configure register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chconf1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_chconf1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_chconf1`] module"]
433pub type RX_CHCONF1 = crate::Reg<rx_chconf1::RX_CHCONF1_SPEC>;
434#[doc = "Channel %s configure register 1"]
435pub mod rx_chconf1;
436#[doc = "TX_CHSTATUS (r) register accessor: Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chstatus::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_chstatus`] module"]
437pub type TX_CHSTATUS = crate::Reg<tx_chstatus::TX_CHSTATUS_SPEC>;
438#[doc = "Channel %s status register"]
439pub mod tx_chstatus;
440#[doc = "RX_CHSTATUS (r) register accessor: Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chstatus::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_chstatus`] module"]
441pub type RX_CHSTATUS = crate::Reg<rx_chstatus::RX_CHSTATUS_SPEC>;
442#[doc = "Channel %s status register"]
443pub mod rx_chstatus;
444#[doc = "INT_RAW (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
445pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
446#[doc = "Raw interrupt status"]
447pub mod int_raw;
448#[doc = "INT_ST (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
449pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
450#[doc = "Masked interrupt status"]
451pub mod int_st;
452#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
453pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
454#[doc = "Interrupt enable bits"]
455pub mod int_ena;
456#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
457pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
458#[doc = "Interrupt clear bits"]
459pub mod int_clr;
460#[doc = "CHCARRIER_DUTY (rw) register accessor: Channel %s duty cycle configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chcarrier_duty::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chcarrier_duty::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chcarrier_duty`] module"]
461pub type CHCARRIER_DUTY = crate::Reg<chcarrier_duty::CHCARRIER_DUTY_SPEC>;
462#[doc = "Channel %s duty cycle configuration register"]
463pub mod chcarrier_duty;
464#[doc = "CH_RX_CARRIER_RM (rw) register accessor: Channel %s carrier remove register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_rx_carrier_rm::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_rx_carrier_rm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_rx_carrier_rm`] module"]
465pub type CH_RX_CARRIER_RM = crate::Reg<ch_rx_carrier_rm::CH_RX_CARRIER_RM_SPEC>;
466#[doc = "Channel %s carrier remove register"]
467pub mod ch_rx_carrier_rm;
468#[doc = "CH_TX_LIM (rw) register accessor: Channel %s Tx event configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_tx_lim::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_tx_lim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_tx_lim`] module"]
469pub type CH_TX_LIM = crate::Reg<ch_tx_lim::CH_TX_LIM_SPEC>;
470#[doc = "Channel %s Tx event configuration register"]
471pub mod ch_tx_lim;
472#[doc = "CH_RX_LIM (rw) register accessor: Channel %s Rx event configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_rx_lim::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_rx_lim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_rx_lim`] module"]
473pub type CH_RX_LIM = crate::Reg<ch_rx_lim::CH_RX_LIM_SPEC>;
474#[doc = "Channel %s Rx event configuration register"]
475pub mod ch_rx_lim;
476#[doc = "SYS_CONF (rw) register accessor: RMT apb configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_conf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_conf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sys_conf`] module"]
477pub type SYS_CONF = crate::Reg<sys_conf::SYS_CONF_SPEC>;
478#[doc = "RMT apb configuration register"]
479pub mod sys_conf;
480#[doc = "TX_SIM (rw) register accessor: RMT TX synchronous register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_sim::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tx_sim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx_sim`] module"]
481pub type TX_SIM = crate::Reg<tx_sim::TX_SIM_SPEC>;
482#[doc = "RMT TX synchronous register"]
483pub mod tx_sim;
484#[doc = "REF_CNT_RST (w) register accessor: RMT clock divider reset register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_cnt_rst::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ref_cnt_rst`] module"]
485pub type REF_CNT_RST = crate::Reg<ref_cnt_rst::REF_CNT_RST_SPEC>;
486#[doc = "RMT clock divider reset register"]
487pub mod ref_cnt_rst;
488#[doc = "DATE (rw) register accessor: RMT version register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
489pub type DATE = crate::Reg<date::DATE_SPEC>;
490#[doc = "RMT version register"]
491pub mod date;
esp32p4/rmt.rs

esp32p4/
rmt.rs
