esp32p4/lp_i2c0/
int_raw.rs1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Field `RXFIFO_WM_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt."]
4pub type RXFIFO_WM_INT_RAW_R = crate::BitReader;
5#[doc = "Field `TXFIFO_WM_INT_RAW` reader - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt."]
6pub type TXFIFO_WM_INT_RAW_R = crate::BitReader;
7#[doc = "Field `RXFIFO_OVF_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt."]
8pub type RXFIFO_OVF_INT_RAW_R = crate::BitReader;
9#[doc = "Field `END_DETECT_INT_RAW` reader - The raw interrupt status of the I2C_END_DETECT_INT interrupt."]
10pub type END_DETECT_INT_RAW_R = crate::BitReader;
11#[doc = "Field `BYTE_TRANS_DONE_INT_RAW` reader - The raw interrupt status of the I2C_END_DETECT_INT interrupt."]
12pub type BYTE_TRANS_DONE_INT_RAW_R = crate::BitReader;
13#[doc = "Field `ARBITRATION_LOST_INT_RAW` reader - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt."]
14pub type ARBITRATION_LOST_INT_RAW_R = crate::BitReader;
15#[doc = "Field `MST_TXFIFO_UDF_INT_RAW` reader - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt."]
16pub type MST_TXFIFO_UDF_INT_RAW_R = crate::BitReader;
17#[doc = "Field `TRANS_COMPLETE_INT_RAW` reader - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt."]
18pub type TRANS_COMPLETE_INT_RAW_R = crate::BitReader;
19#[doc = "Field `TIME_OUT_INT_RAW` reader - The raw interrupt status of the I2C_TIME_OUT_INT interrupt."]
20pub type TIME_OUT_INT_RAW_R = crate::BitReader;
21#[doc = "Field `TRANS_START_INT_RAW` reader - The raw interrupt status of the I2C_TRANS_START_INT interrupt."]
22pub type TRANS_START_INT_RAW_R = crate::BitReader;
23#[doc = "Field `NACK_INT_RAW` reader - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."]
24pub type NACK_INT_RAW_R = crate::BitReader;
25#[doc = "Field `TXFIFO_OVF_INT_RAW` reader - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt."]
26pub type TXFIFO_OVF_INT_RAW_R = crate::BitReader;
27#[doc = "Field `RXFIFO_UDF_INT_RAW` reader - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt."]
28pub type RXFIFO_UDF_INT_RAW_R = crate::BitReader;
29#[doc = "Field `SCL_ST_TO_INT_RAW` reader - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt."]
30pub type SCL_ST_TO_INT_RAW_R = crate::BitReader;
31#[doc = "Field `SCL_MAIN_ST_TO_INT_RAW` reader - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt."]
32pub type SCL_MAIN_ST_TO_INT_RAW_R = crate::BitReader;
33#[doc = "Field `DET_START_INT_RAW` reader - The raw interrupt status of I2C_DET_START_INT interrupt."]
34pub type DET_START_INT_RAW_R = crate::BitReader;
35impl R {
36 #[doc = "Bit 0 - The raw interrupt status of I2C_RXFIFO_WM_INT interrupt."]
37 #[inline(always)]
38 pub fn rxfifo_wm_int_raw(&self) -> RXFIFO_WM_INT_RAW_R {
39 RXFIFO_WM_INT_RAW_R::new((self.bits & 1) != 0)
40 }
41 #[doc = "Bit 1 - The raw interrupt status of I2C_TXFIFO_WM_INT interrupt."]
42 #[inline(always)]
43 pub fn txfifo_wm_int_raw(&self) -> TXFIFO_WM_INT_RAW_R {
44 TXFIFO_WM_INT_RAW_R::new(((self.bits >> 1) & 1) != 0)
45 }
46 #[doc = "Bit 2 - The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt."]
47 #[inline(always)]
48 pub fn rxfifo_ovf_int_raw(&self) -> RXFIFO_OVF_INT_RAW_R {
49 RXFIFO_OVF_INT_RAW_R::new(((self.bits >> 2) & 1) != 0)
50 }
51 #[doc = "Bit 3 - The raw interrupt status of the I2C_END_DETECT_INT interrupt."]
52 #[inline(always)]
53 pub fn end_detect_int_raw(&self) -> END_DETECT_INT_RAW_R {
54 END_DETECT_INT_RAW_R::new(((self.bits >> 3) & 1) != 0)
55 }
56 #[doc = "Bit 4 - The raw interrupt status of the I2C_END_DETECT_INT interrupt."]
57 #[inline(always)]
58 pub fn byte_trans_done_int_raw(&self) -> BYTE_TRANS_DONE_INT_RAW_R {
59 BYTE_TRANS_DONE_INT_RAW_R::new(((self.bits >> 4) & 1) != 0)
60 }
61 #[doc = "Bit 5 - The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt."]
62 #[inline(always)]
63 pub fn arbitration_lost_int_raw(&self) -> ARBITRATION_LOST_INT_RAW_R {
64 ARBITRATION_LOST_INT_RAW_R::new(((self.bits >> 5) & 1) != 0)
65 }
66 #[doc = "Bit 6 - The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt."]
67 #[inline(always)]
68 pub fn mst_txfifo_udf_int_raw(&self) -> MST_TXFIFO_UDF_INT_RAW_R {
69 MST_TXFIFO_UDF_INT_RAW_R::new(((self.bits >> 6) & 1) != 0)
70 }
71 #[doc = "Bit 7 - The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt."]
72 #[inline(always)]
73 pub fn trans_complete_int_raw(&self) -> TRANS_COMPLETE_INT_RAW_R {
74 TRANS_COMPLETE_INT_RAW_R::new(((self.bits >> 7) & 1) != 0)
75 }
76 #[doc = "Bit 8 - The raw interrupt status of the I2C_TIME_OUT_INT interrupt."]
77 #[inline(always)]
78 pub fn time_out_int_raw(&self) -> TIME_OUT_INT_RAW_R {
79 TIME_OUT_INT_RAW_R::new(((self.bits >> 8) & 1) != 0)
80 }
81 #[doc = "Bit 9 - The raw interrupt status of the I2C_TRANS_START_INT interrupt."]
82 #[inline(always)]
83 pub fn trans_start_int_raw(&self) -> TRANS_START_INT_RAW_R {
84 TRANS_START_INT_RAW_R::new(((self.bits >> 9) & 1) != 0)
85 }
86 #[doc = "Bit 10 - The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt."]
87 #[inline(always)]
88 pub fn nack_int_raw(&self) -> NACK_INT_RAW_R {
89 NACK_INT_RAW_R::new(((self.bits >> 10) & 1) != 0)
90 }
91 #[doc = "Bit 11 - The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt."]
92 #[inline(always)]
93 pub fn txfifo_ovf_int_raw(&self) -> TXFIFO_OVF_INT_RAW_R {
94 TXFIFO_OVF_INT_RAW_R::new(((self.bits >> 11) & 1) != 0)
95 }
96 #[doc = "Bit 12 - The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt."]
97 #[inline(always)]
98 pub fn rxfifo_udf_int_raw(&self) -> RXFIFO_UDF_INT_RAW_R {
99 RXFIFO_UDF_INT_RAW_R::new(((self.bits >> 12) & 1) != 0)
100 }
101 #[doc = "Bit 13 - The raw interrupt status of I2C_SCL_ST_TO_INT interrupt."]
102 #[inline(always)]
103 pub fn scl_st_to_int_raw(&self) -> SCL_ST_TO_INT_RAW_R {
104 SCL_ST_TO_INT_RAW_R::new(((self.bits >> 13) & 1) != 0)
105 }
106 #[doc = "Bit 14 - The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt."]
107 #[inline(always)]
108 pub fn scl_main_st_to_int_raw(&self) -> SCL_MAIN_ST_TO_INT_RAW_R {
109 SCL_MAIN_ST_TO_INT_RAW_R::new(((self.bits >> 14) & 1) != 0)
110 }
111 #[doc = "Bit 15 - The raw interrupt status of I2C_DET_START_INT interrupt."]
112 #[inline(always)]
113 pub fn det_start_int_raw(&self) -> DET_START_INT_RAW_R {
114 DET_START_INT_RAW_R::new(((self.bits >> 15) & 1) != 0)
115 }
116}
117#[cfg(feature = "impl-register-debug")]
118impl core::fmt::Debug for R {
119 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
120 f.debug_struct("INT_RAW")
121 .field(
122 "rxfifo_wm_int_raw",
123 &format_args!("{}", self.rxfifo_wm_int_raw().bit()),
124 )
125 .field(
126 "txfifo_wm_int_raw",
127 &format_args!("{}", self.txfifo_wm_int_raw().bit()),
128 )
129 .field(
130 "rxfifo_ovf_int_raw",
131 &format_args!("{}", self.rxfifo_ovf_int_raw().bit()),
132 )
133 .field(
134 "end_detect_int_raw",
135 &format_args!("{}", self.end_detect_int_raw().bit()),
136 )
137 .field(
138 "byte_trans_done_int_raw",
139 &format_args!("{}", self.byte_trans_done_int_raw().bit()),
140 )
141 .field(
142 "arbitration_lost_int_raw",
143 &format_args!("{}", self.arbitration_lost_int_raw().bit()),
144 )
145 .field(
146 "mst_txfifo_udf_int_raw",
147 &format_args!("{}", self.mst_txfifo_udf_int_raw().bit()),
148 )
149 .field(
150 "trans_complete_int_raw",
151 &format_args!("{}", self.trans_complete_int_raw().bit()),
152 )
153 .field(
154 "time_out_int_raw",
155 &format_args!("{}", self.time_out_int_raw().bit()),
156 )
157 .field(
158 "trans_start_int_raw",
159 &format_args!("{}", self.trans_start_int_raw().bit()),
160 )
161 .field(
162 "nack_int_raw",
163 &format_args!("{}", self.nack_int_raw().bit()),
164 )
165 .field(
166 "txfifo_ovf_int_raw",
167 &format_args!("{}", self.txfifo_ovf_int_raw().bit()),
168 )
169 .field(
170 "rxfifo_udf_int_raw",
171 &format_args!("{}", self.rxfifo_udf_int_raw().bit()),
172 )
173 .field(
174 "scl_st_to_int_raw",
175 &format_args!("{}", self.scl_st_to_int_raw().bit()),
176 )
177 .field(
178 "scl_main_st_to_int_raw",
179 &format_args!("{}", self.scl_main_st_to_int_raw().bit()),
180 )
181 .field(
182 "det_start_int_raw",
183 &format_args!("{}", self.det_start_int_raw().bit()),
184 )
185 .finish()
186 }
187}
188#[cfg(feature = "impl-register-debug")]
189impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
190 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
191 core::fmt::Debug::fmt(&self.read(), f)
192 }
193}
194#[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
195pub struct INT_RAW_SPEC;
196impl crate::RegisterSpec for INT_RAW_SPEC {
197 type Ux = u32;
198}
199#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
200impl crate::Readable for INT_RAW_SPEC {}
201#[doc = "`reset()` method sets INT_RAW to value 0x02"]
202impl crate::Resettable for INT_RAW_SPEC {
203 const RESET_VALUE: u32 = 0x02;
204}