1#[doc = "Register `DIN_MODE` reader"]
2pub type R = crate::R<DIN_MODE_SPEC>;
3#[doc = "Register `DIN_MODE` writer"]
4pub type W = crate::W<DIN_MODE_SPEC>;
5#[doc = "Field `DIN0_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
6pub type DIN0_MODE_R = crate::FieldReader;
7#[doc = "Field `DIN0_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
8pub type DIN0_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `DIN1_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
10pub type DIN1_MODE_R = crate::FieldReader;
11#[doc = "Field `DIN1_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
12pub type DIN1_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `DIN2_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
14pub type DIN2_MODE_R = crate::FieldReader;
15#[doc = "Field `DIN2_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
16pub type DIN2_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `DIN3_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
18pub type DIN3_MODE_R = crate::FieldReader;
19#[doc = "Field `DIN3_MODE` writer - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
20pub type DIN3_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `DIN4_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
22pub type DIN4_MODE_R = crate::FieldReader;
23#[doc = "Field `DIN5_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state."]
24pub type DIN5_MODE_R = crate::FieldReader;
25#[doc = "Field `DIN6_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state."]
26pub type DIN6_MODE_R = crate::FieldReader;
27#[doc = "Field `DIN7_MODE` reader - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state."]
28pub type DIN7_MODE_R = crate::FieldReader;
29#[doc = "Field `TIMING_HCLK_ACTIVE` reader - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
30pub type TIMING_HCLK_ACTIVE_R = crate::BitReader;
31#[doc = "Field `TIMING_HCLK_ACTIVE` writer - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
32pub type TIMING_HCLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34 #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
35 #[inline(always)]
36 pub fn din0_mode(&self) -> DIN0_MODE_R {
37 DIN0_MODE_R::new((self.bits & 3) as u8)
38 }
39 #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
40 #[inline(always)]
41 pub fn din1_mode(&self) -> DIN1_MODE_R {
42 DIN1_MODE_R::new(((self.bits >> 2) & 3) as u8)
43 }
44 #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
45 #[inline(always)]
46 pub fn din2_mode(&self) -> DIN2_MODE_R {
47 DIN2_MODE_R::new(((self.bits >> 4) & 3) as u8)
48 }
49 #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
50 #[inline(always)]
51 pub fn din3_mode(&self) -> DIN3_MODE_R {
52 DIN3_MODE_R::new(((self.bits >> 6) & 3) as u8)
53 }
54 #[doc = "Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
55 #[inline(always)]
56 pub fn din4_mode(&self) -> DIN4_MODE_R {
57 DIN4_MODE_R::new(((self.bits >> 8) & 3) as u8)
58 }
59 #[doc = "Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state."]
60 #[inline(always)]
61 pub fn din5_mode(&self) -> DIN5_MODE_R {
62 DIN5_MODE_R::new(((self.bits >> 10) & 3) as u8)
63 }
64 #[doc = "Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state."]
65 #[inline(always)]
66 pub fn din6_mode(&self) -> DIN6_MODE_R {
67 DIN6_MODE_R::new(((self.bits >> 12) & 3) as u8)
68 }
69 #[doc = "Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state."]
70 #[inline(always)]
71 pub fn din7_mode(&self) -> DIN7_MODE_R {
72 DIN7_MODE_R::new(((self.bits >> 14) & 3) as u8)
73 }
74 #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
75 #[inline(always)]
76 pub fn timing_hclk_active(&self) -> TIMING_HCLK_ACTIVE_R {
77 TIMING_HCLK_ACTIVE_R::new(((self.bits >> 16) & 1) != 0)
78 }
79}
80#[cfg(feature = "impl-register-debug")]
81impl core::fmt::Debug for R {
82 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
83 f.debug_struct("DIN_MODE")
84 .field("din0_mode", &self.din0_mode())
85 .field("din1_mode", &self.din1_mode())
86 .field("din2_mode", &self.din2_mode())
87 .field("din3_mode", &self.din3_mode())
88 .field("din4_mode", &self.din4_mode())
89 .field("din5_mode", &self.din5_mode())
90 .field("din6_mode", &self.din6_mode())
91 .field("din7_mode", &self.din7_mode())
92 .field("timing_hclk_active", &self.timing_hclk_active())
93 .finish()
94 }
95}
96impl W {
97 #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
98 #[inline(always)]
99 pub fn din0_mode(&mut self) -> DIN0_MODE_W<DIN_MODE_SPEC> {
100 DIN0_MODE_W::new(self, 0)
101 }
102 #[doc = "Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
103 #[inline(always)]
104 pub fn din1_mode(&mut self) -> DIN1_MODE_W<DIN_MODE_SPEC> {
105 DIN1_MODE_W::new(self, 2)
106 }
107 #[doc = "Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
108 #[inline(always)]
109 pub fn din2_mode(&mut self) -> DIN2_MODE_W<DIN_MODE_SPEC> {
110 DIN2_MODE_W::new(self, 4)
111 }
112 #[doc = "Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
113 #[inline(always)]
114 pub fn din3_mode(&mut self) -> DIN3_MODE_W<DIN_MODE_SPEC> {
115 DIN3_MODE_W::new(self, 6)
116 }
117 #[doc = "Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state."]
118 #[inline(always)]
119 pub fn timing_hclk_active(&mut self) -> TIMING_HCLK_ACTIVE_W<DIN_MODE_SPEC> {
120 TIMING_HCLK_ACTIVE_W::new(self, 16)
121 }
122}
123#[doc = "SPI input delay mode configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`din_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`din_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
124pub struct DIN_MODE_SPEC;
125impl crate::RegisterSpec for DIN_MODE_SPEC {
126 type Ux = u32;
127}
128#[doc = "`read()` method returns [`din_mode::R`](R) reader structure"]
129impl crate::Readable for DIN_MODE_SPEC {}
130#[doc = "`write(|w| ..)` method takes [`din_mode::W`](W) writer structure"]
131impl crate::Writable for DIN_MODE_SPEC {
132 type Safety = crate::Unsafe;
133 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
134 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
135}
136#[doc = "`reset()` method sets DIN_MODE to value 0"]
137impl crate::Resettable for DIN_MODE_SPEC {
138 const RESET_VALUE: u32 = 0;
139}