1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `DUMMY_OUT` reader - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
6pub type DUMMY_OUT_R = crate::BitReader;
7#[doc = "Field `DUMMY_OUT` writer - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
8pub type DUMMY_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FADDR_DUAL` reader - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
10pub type FADDR_DUAL_R = crate::BitReader;
11#[doc = "Field `FADDR_DUAL` writer - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
12pub type FADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FADDR_QUAD` reader - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
14pub type FADDR_QUAD_R = crate::BitReader;
15#[doc = "Field `FADDR_QUAD` writer - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
16pub type FADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FADDR_OCT` reader - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
18pub type FADDR_OCT_R = crate::BitReader;
19#[doc = "Field `FCMD_DUAL` reader - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
20pub type FCMD_DUAL_R = crate::BitReader;
21#[doc = "Field `FCMD_DUAL` writer - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
22pub type FCMD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
24pub type FCMD_QUAD_R = crate::BitReader;
25#[doc = "Field `FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
26pub type FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `FCMD_OCT` reader - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
28pub type FCMD_OCT_R = crate::BitReader;
29#[doc = "Field `FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."]
30pub type FREAD_DUAL_R = crate::BitReader;
31#[doc = "Field `FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."]
32pub type FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."]
34pub type FREAD_QUAD_R = crate::BitReader;
35#[doc = "Field `FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."]
36pub type FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FREAD_OCT` reader - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state."]
38pub type FREAD_OCT_R = crate::BitReader;
39#[doc = "Field `Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
40pub type Q_POL_R = crate::BitReader;
41#[doc = "Field `Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
42pub type Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
44pub type D_POL_R = crate::BitReader;
45#[doc = "Field `D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
46pub type D_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `HOLD_POL` reader - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
48pub type HOLD_POL_R = crate::BitReader;
49#[doc = "Field `HOLD_POL` writer - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
50pub type HOLD_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
51#[doc = "Field `WP_POL` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
52pub type WP_POL_R = crate::BitReader;
53#[doc = "Field `WP_POL` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
54pub type WP_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
55#[doc = "Field `RD_BIT_ORDER` reader - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
56pub type RD_BIT_ORDER_R = crate::FieldReader;
57#[doc = "Field `RD_BIT_ORDER` writer - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
58pub type RD_BIT_ORDER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
59#[doc = "Field `WR_BIT_ORDER` reader - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
60pub type WR_BIT_ORDER_R = crate::FieldReader;
61#[doc = "Field `WR_BIT_ORDER` writer - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
62pub type WR_BIT_ORDER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
63impl R {
64 #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
65 #[inline(always)]
66 pub fn dummy_out(&self) -> DUMMY_OUT_R {
67 DUMMY_OUT_R::new(((self.bits >> 3) & 1) != 0)
68 }
69 #[doc = "Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
70 #[inline(always)]
71 pub fn faddr_dual(&self) -> FADDR_DUAL_R {
72 FADDR_DUAL_R::new(((self.bits >> 5) & 1) != 0)
73 }
74 #[doc = "Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
75 #[inline(always)]
76 pub fn faddr_quad(&self) -> FADDR_QUAD_R {
77 FADDR_QUAD_R::new(((self.bits >> 6) & 1) != 0)
78 }
79 #[doc = "Bit 7 - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
80 #[inline(always)]
81 pub fn faddr_oct(&self) -> FADDR_OCT_R {
82 FADDR_OCT_R::new(((self.bits >> 7) & 1) != 0)
83 }
84 #[doc = "Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
85 #[inline(always)]
86 pub fn fcmd_dual(&self) -> FCMD_DUAL_R {
87 FCMD_DUAL_R::new(((self.bits >> 8) & 1) != 0)
88 }
89 #[doc = "Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
90 #[inline(always)]
91 pub fn fcmd_quad(&self) -> FCMD_QUAD_R {
92 FCMD_QUAD_R::new(((self.bits >> 9) & 1) != 0)
93 }
94 #[doc = "Bit 10 - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
95 #[inline(always)]
96 pub fn fcmd_oct(&self) -> FCMD_OCT_R {
97 FCMD_OCT_R::new(((self.bits >> 10) & 1) != 0)
98 }
99 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."]
100 #[inline(always)]
101 pub fn fread_dual(&self) -> FREAD_DUAL_R {
102 FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0)
103 }
104 #[doc = "Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."]
105 #[inline(always)]
106 pub fn fread_quad(&self) -> FREAD_QUAD_R {
107 FREAD_QUAD_R::new(((self.bits >> 15) & 1) != 0)
108 }
109 #[doc = "Bit 16 - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state."]
110 #[inline(always)]
111 pub fn fread_oct(&self) -> FREAD_OCT_R {
112 FREAD_OCT_R::new(((self.bits >> 16) & 1) != 0)
113 }
114 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
115 #[inline(always)]
116 pub fn q_pol(&self) -> Q_POL_R {
117 Q_POL_R::new(((self.bits >> 18) & 1) != 0)
118 }
119 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
120 #[inline(always)]
121 pub fn d_pol(&self) -> D_POL_R {
122 D_POL_R::new(((self.bits >> 19) & 1) != 0)
123 }
124 #[doc = "Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
125 #[inline(always)]
126 pub fn hold_pol(&self) -> HOLD_POL_R {
127 HOLD_POL_R::new(((self.bits >> 20) & 1) != 0)
128 }
129 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
130 #[inline(always)]
131 pub fn wp_pol(&self) -> WP_POL_R {
132 WP_POL_R::new(((self.bits >> 21) & 1) != 0)
133 }
134 #[doc = "Bits 23:24 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
135 #[inline(always)]
136 pub fn rd_bit_order(&self) -> RD_BIT_ORDER_R {
137 RD_BIT_ORDER_R::new(((self.bits >> 23) & 3) as u8)
138 }
139 #[doc = "Bits 25:26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
140 #[inline(always)]
141 pub fn wr_bit_order(&self) -> WR_BIT_ORDER_R {
142 WR_BIT_ORDER_R::new(((self.bits >> 25) & 3) as u8)
143 }
144}
145#[cfg(feature = "impl-register-debug")]
146impl core::fmt::Debug for R {
147 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
148 f.debug_struct("CTRL")
149 .field("dummy_out", &self.dummy_out())
150 .field("faddr_dual", &self.faddr_dual())
151 .field("faddr_quad", &self.faddr_quad())
152 .field("faddr_oct", &self.faddr_oct())
153 .field("fcmd_dual", &self.fcmd_dual())
154 .field("fcmd_quad", &self.fcmd_quad())
155 .field("fcmd_oct", &self.fcmd_oct())
156 .field("fread_dual", &self.fread_dual())
157 .field("fread_quad", &self.fread_quad())
158 .field("fread_oct", &self.fread_oct())
159 .field("q_pol", &self.q_pol())
160 .field("d_pol", &self.d_pol())
161 .field("hold_pol", &self.hold_pol())
162 .field("wp_pol", &self.wp_pol())
163 .field("rd_bit_order", &self.rd_bit_order())
164 .field("wr_bit_order", &self.wr_bit_order())
165 .finish()
166 }
167}
168impl W {
169 #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
170 #[inline(always)]
171 pub fn dummy_out(&mut self) -> DUMMY_OUT_W<CTRL_SPEC> {
172 DUMMY_OUT_W::new(self, 3)
173 }
174 #[doc = "Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
175 #[inline(always)]
176 pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<CTRL_SPEC> {
177 FADDR_DUAL_W::new(self, 5)
178 }
179 #[doc = "Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state."]
180 #[inline(always)]
181 pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<CTRL_SPEC> {
182 FADDR_QUAD_W::new(self, 6)
183 }
184 #[doc = "Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
185 #[inline(always)]
186 pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<CTRL_SPEC> {
187 FCMD_DUAL_W::new(self, 8)
188 }
189 #[doc = "Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state."]
190 #[inline(always)]
191 pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
192 FCMD_QUAD_W::new(self, 9)
193 }
194 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state."]
195 #[inline(always)]
196 pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
197 FREAD_DUAL_W::new(self, 14)
198 }
199 #[doc = "Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state."]
200 #[inline(always)]
201 pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
202 FREAD_QUAD_W::new(self, 15)
203 }
204 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state."]
205 #[inline(always)]
206 pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
207 Q_POL_W::new(self, 18)
208 }
209 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state."]
210 #[inline(always)]
211 pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
212 D_POL_W::new(self, 19)
213 }
214 #[doc = "Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
215 #[inline(always)]
216 pub fn hold_pol(&mut self) -> HOLD_POL_W<CTRL_SPEC> {
217 HOLD_POL_W::new(self, 20)
218 }
219 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state."]
220 #[inline(always)]
221 pub fn wp_pol(&mut self) -> WP_POL_W<CTRL_SPEC> {
222 WP_POL_W::new(self, 21)
223 }
224 #[doc = "Bits 23:24 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state."]
225 #[inline(always)]
226 pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<CTRL_SPEC> {
227 RD_BIT_ORDER_W::new(self, 23)
228 }
229 #[doc = "Bits 25:26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state."]
230 #[inline(always)]
231 pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<CTRL_SPEC> {
232 WR_BIT_ORDER_W::new(self, 25)
233 }
234}
235#[doc = "SPI control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
236pub struct CTRL_SPEC;
237impl crate::RegisterSpec for CTRL_SPEC {
238 type Ux = u32;
239}
240#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
241impl crate::Readable for CTRL_SPEC {}
242#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
243impl crate::Writable for CTRL_SPEC {
244 type Safety = crate::Unsafe;
245 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
246 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
247}
248#[doc = "`reset()` method sets CTRL to value 0x003c_0000"]
249impl crate::Resettable for CTRL_SPEC {
250 const RESET_VALUE: u32 = 0x003c_0000;
251}