1#[doc = "Register `CLOCK` reader"]
2pub type R = crate::R<CLOCK_SPEC>;
3#[doc = "Register `CLOCK` writer"]
4pub type W = crate::W<CLOCK_SPEC>;
5#[doc = "Field `CLKCNT_L` reader - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
6pub type CLKCNT_L_R = crate::FieldReader;
7#[doc = "Field `CLKCNT_L` writer - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
8pub type CLKCNT_L_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `CLKCNT_H` reader - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."]
10pub type CLKCNT_H_R = crate::FieldReader;
11#[doc = "Field `CLKCNT_H` writer - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."]
12pub type CLKCNT_H_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `CLKCNT_N` reader - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."]
14pub type CLKCNT_N_R = crate::FieldReader;
15#[doc = "Field `CLKCNT_N` writer - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."]
16pub type CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `CLKDIV_PRE` reader - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."]
18pub type CLKDIV_PRE_R = crate::FieldReader;
19#[doc = "Field `CLKDIV_PRE` writer - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."]
20pub type CLKDIV_PRE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `CLK_EQU_SYSCLK` reader - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."]
22pub type CLK_EQU_SYSCLK_R = crate::BitReader;
23#[doc = "Field `CLK_EQU_SYSCLK` writer - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."]
24pub type CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26 #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
27 #[inline(always)]
28 pub fn clkcnt_l(&self) -> CLKCNT_L_R {
29 CLKCNT_L_R::new((self.bits & 0x3f) as u8)
30 }
31 #[doc = "Bits 6:11 - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."]
32 #[inline(always)]
33 pub fn clkcnt_h(&self) -> CLKCNT_H_R {
34 CLKCNT_H_R::new(((self.bits >> 6) & 0x3f) as u8)
35 }
36 #[doc = "Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."]
37 #[inline(always)]
38 pub fn clkcnt_n(&self) -> CLKCNT_N_R {
39 CLKCNT_N_R::new(((self.bits >> 12) & 0x3f) as u8)
40 }
41 #[doc = "Bits 18:21 - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."]
42 #[inline(always)]
43 pub fn clkdiv_pre(&self) -> CLKDIV_PRE_R {
44 CLKDIV_PRE_R::new(((self.bits >> 18) & 0x0f) as u8)
45 }
46 #[doc = "Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."]
47 #[inline(always)]
48 pub fn clk_equ_sysclk(&self) -> CLK_EQU_SYSCLK_R {
49 CLK_EQU_SYSCLK_R::new(((self.bits >> 31) & 1) != 0)
50 }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55 f.debug_struct("CLOCK")
56 .field("clkcnt_l", &self.clkcnt_l())
57 .field("clkcnt_h", &self.clkcnt_h())
58 .field("clkcnt_n", &self.clkcnt_n())
59 .field("clkdiv_pre", &self.clkdiv_pre())
60 .field("clk_equ_sysclk", &self.clk_equ_sysclk())
61 .finish()
62 }
63}
64impl W {
65 #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
66 #[inline(always)]
67 pub fn clkcnt_l(&mut self) -> CLKCNT_L_W<CLOCK_SPEC> {
68 CLKCNT_L_W::new(self, 0)
69 }
70 #[doc = "Bits 6:11 - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state."]
71 #[inline(always)]
72 pub fn clkcnt_h(&mut self) -> CLKCNT_H_W<CLOCK_SPEC> {
73 CLKCNT_H_W::new(self, 6)
74 }
75 #[doc = "Bits 12:17 - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state."]
76 #[inline(always)]
77 pub fn clkcnt_n(&mut self) -> CLKCNT_N_W<CLOCK_SPEC> {
78 CLKCNT_N_W::new(self, 12)
79 }
80 #[doc = "Bits 18:21 - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state."]
81 #[inline(always)]
82 pub fn clkdiv_pre(&mut self) -> CLKDIV_PRE_W<CLOCK_SPEC> {
83 CLKDIV_PRE_W::new(self, 18)
84 }
85 #[doc = "Bit 31 - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state."]
86 #[inline(always)]
87 pub fn clk_equ_sysclk(&mut self) -> CLK_EQU_SYSCLK_W<CLOCK_SPEC> {
88 CLK_EQU_SYSCLK_W::new(self, 31)
89 }
90}
91#[doc = "SPI clock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`clock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct CLOCK_SPEC;
93impl crate::RegisterSpec for CLOCK_SPEC {
94 type Ux = u32;
95}
96#[doc = "`read()` method returns [`clock::R`](R) reader structure"]
97impl crate::Readable for CLOCK_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`clock::W`](W) writer structure"]
99impl crate::Writable for CLOCK_SPEC {
100 type Safety = crate::Unsafe;
101 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets CLOCK to value 0x8000_3043"]
105impl crate::Resettable for CLOCK_SPEC {
106 const RESET_VALUE: u32 = 0x8000_3043;
107}