Expand description
SPI module clock and register clock control
Structs§
- CLK_
GATE_ SPEC - SPI module clock and register clock control
Type Aliases§
- CLK_
EN_ R - Field
CLK_EN
reader - Set this bit to enable clk gate - CLK_
EN_ W - Field
CLK_EN
writer - Set this bit to enable clk gate - MST_
CLK_ ACTIVE_ R - Field
MST_CLK_ACTIVE
reader - Set this bit to power on the SPI module clock. - MST_
CLK_ ACTIVE_ W - Field
MST_CLK_ACTIVE
writer - Set this bit to power on the SPI module clock. - MST_
CLK_ SEL_ R - Field
MST_CLK_SEL
reader - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. - MST_
CLK_ SEL_ W - Field
MST_CLK_SEL
writer - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. - R
- Register
CLK_GATE
reader - W
- Register
CLK_GATE
writer