esp32h2/spi1/
int_ena.rs

1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `PER_END` reader - The enable bit for SPI_MEM_PER_END_INT interrupt."]
6pub type PER_END_R = crate::BitReader;
7#[doc = "Field `PER_END` writer - The enable bit for SPI_MEM_PER_END_INT interrupt."]
8pub type PER_END_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PES_END` reader - The enable bit for SPI_MEM_PES_END_INT interrupt."]
10pub type PES_END_R = crate::BitReader;
11#[doc = "Field `PES_END` writer - The enable bit for SPI_MEM_PES_END_INT interrupt."]
12pub type PES_END_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `WPE_END` reader - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
14pub type WPE_END_R = crate::BitReader;
15#[doc = "Field `WPE_END` writer - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
16pub type WPE_END_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SLV_ST_END` reader - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
18pub type SLV_ST_END_R = crate::BitReader;
19#[doc = "Field `SLV_ST_END` writer - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
20pub type SLV_ST_END_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MST_ST_END` reader - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
22pub type MST_ST_END_R = crate::BitReader;
23#[doc = "Field `MST_ST_END` writer - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
24pub type MST_ST_END_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `BROWN_OUT` reader - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."]
26pub type BROWN_OUT_R = crate::BitReader;
27#[doc = "Field `BROWN_OUT` writer - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."]
28pub type BROWN_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
31    #[inline(always)]
32    pub fn per_end(&self) -> PER_END_R {
33        PER_END_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - The enable bit for SPI_MEM_PES_END_INT interrupt."]
36    #[inline(always)]
37    pub fn pes_end(&self) -> PES_END_R {
38        PES_END_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
41    #[inline(always)]
42    pub fn wpe_end(&self) -> WPE_END_R {
43        WPE_END_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
46    #[inline(always)]
47    pub fn slv_st_end(&self) -> SLV_ST_END_R {
48        SLV_ST_END_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
51    #[inline(always)]
52    pub fn mst_st_end(&self) -> MST_ST_END_R {
53        MST_ST_END_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 10 - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."]
56    #[inline(always)]
57    pub fn brown_out(&self) -> BROWN_OUT_R {
58        BROWN_OUT_R::new(((self.bits >> 10) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("INT_ENA")
65            .field("per_end", &self.per_end())
66            .field("pes_end", &self.pes_end())
67            .field("wpe_end", &self.wpe_end())
68            .field("slv_st_end", &self.slv_st_end())
69            .field("mst_st_end", &self.mst_st_end())
70            .field("brown_out", &self.brown_out())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
76    #[inline(always)]
77    pub fn per_end(&mut self) -> PER_END_W<INT_ENA_SPEC> {
78        PER_END_W::new(self, 0)
79    }
80    #[doc = "Bit 1 - The enable bit for SPI_MEM_PES_END_INT interrupt."]
81    #[inline(always)]
82    pub fn pes_end(&mut self) -> PES_END_W<INT_ENA_SPEC> {
83        PES_END_W::new(self, 1)
84    }
85    #[doc = "Bit 2 - The enable bit for SPI_MEM_WPE_END_INT interrupt."]
86    #[inline(always)]
87    pub fn wpe_end(&mut self) -> WPE_END_W<INT_ENA_SPEC> {
88        WPE_END_W::new(self, 2)
89    }
90    #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
91    #[inline(always)]
92    pub fn slv_st_end(&mut self) -> SLV_ST_END_W<INT_ENA_SPEC> {
93        SLV_ST_END_W::new(self, 3)
94    }
95    #[doc = "Bit 4 - The enable bit for SPI_MEM_MST_ST_END_INT interrupt."]
96    #[inline(always)]
97    pub fn mst_st_end(&mut self) -> MST_ST_END_W<INT_ENA_SPEC> {
98        MST_ST_END_W::new(self, 4)
99    }
100    #[doc = "Bit 10 - The enable bit for SPI_MEM_BROWN_OUT_INT interrupt."]
101    #[inline(always)]
102    pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_SPEC> {
103        BROWN_OUT_W::new(self, 10)
104    }
105}
106#[doc = "SPI1 interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct INT_ENA_SPEC;
108impl crate::RegisterSpec for INT_ENA_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
112impl crate::Readable for INT_ENA_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
114impl crate::Writable for INT_ENA_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets INT_ENA to value 0"]
120impl crate::Resettable for INT_ENA_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
esp32h2/spi1/int_ena.rs

esp32h2/spi1/
int_ena.rs
