1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 key: [KEY; 8],
6 text_in: [TEXT_IN; 4],
7 text_out: [TEXT_OUT; 4],
8 mode: MODE,
9 endian: ENDIAN,
10 trigger: TRIGGER,
11 state: STATE,
12 iv_mem: [IV_MEM; 4],
13 h_mem: [H_MEM; 4],
14 j0_mem: [J0_MEM; 4],
15 t0_mem: [T0_MEM; 4],
16 dma_enable: DMA_ENABLE,
17 block_mode: BLOCK_MODE,
18 block_num: BLOCK_NUM,
19 inc_sel: INC_SEL,
20 aad_block_num: AAD_BLOCK_NUM,
21 remainder_bit_num: REMAINDER_BIT_NUM,
22 continue_: CONTINUE,
23 int_clr: INT_CLR,
24 int_ena: INT_ENA,
25 date: DATE,
26 dma_exit: DMA_EXIT,
27}
28impl RegisterBlock {
29 #[doc = "0x00..0x20 - Key material key_%s configure register"]
30 #[inline(always)]
31 pub const fn key(&self, n: usize) -> &KEY {
32 &self.key[n]
33 }
34 #[doc = "Iterator for array of:"]
35 #[doc = "0x00..0x20 - Key material key_%s configure register"]
36 #[inline(always)]
37 pub fn key_iter(&self) -> impl Iterator<Item = &KEY> {
38 self.key.iter()
39 }
40 #[doc = "0x20..0x30 - source text material text_in_%s configure register"]
41 #[inline(always)]
42 pub const fn text_in(&self, n: usize) -> &TEXT_IN {
43 &self.text_in[n]
44 }
45 #[doc = "Iterator for array of:"]
46 #[doc = "0x20..0x30 - source text material text_in_%s configure register"]
47 #[inline(always)]
48 pub fn text_in_iter(&self) -> impl Iterator<Item = &TEXT_IN> {
49 self.text_in.iter()
50 }
51 #[doc = "0x30..0x40 - result text material text_out_%s configure register"]
52 #[inline(always)]
53 pub const fn text_out(&self, n: usize) -> &TEXT_OUT {
54 &self.text_out[n]
55 }
56 #[doc = "Iterator for array of:"]
57 #[doc = "0x30..0x40 - result text material text_out_%s configure register"]
58 #[inline(always)]
59 pub fn text_out_iter(&self) -> impl Iterator<Item = &TEXT_OUT> {
60 self.text_out.iter()
61 }
62 #[doc = "0x40 - AES Mode register"]
63 #[inline(always)]
64 pub const fn mode(&self) -> &MODE {
65 &self.mode
66 }
67 #[doc = "0x44 - AES Endian configure register"]
68 #[inline(always)]
69 pub const fn endian(&self) -> &ENDIAN {
70 &self.endian
71 }
72 #[doc = "0x48 - AES trigger register"]
73 #[inline(always)]
74 pub const fn trigger(&self) -> &TRIGGER {
75 &self.trigger
76 }
77 #[doc = "0x4c - AES state register"]
78 #[inline(always)]
79 pub const fn state(&self) -> &STATE {
80 &self.state
81 }
82 #[doc = "0x50..0x60 - The memory that stores initialization vector"]
83 #[inline(always)]
84 pub const fn iv_mem(&self, n: usize) -> &IV_MEM {
85 &self.iv_mem[n]
86 }
87 #[doc = "Iterator for array of:"]
88 #[doc = "0x50..0x60 - The memory that stores initialization vector"]
89 #[inline(always)]
90 pub fn iv_mem_iter(&self) -> impl Iterator<Item = &IV_MEM> {
91 self.iv_mem.iter()
92 }
93 #[doc = "0x60..0x70 - The memory that stores GCM hash subkey"]
94 #[inline(always)]
95 pub const fn h_mem(&self, n: usize) -> &H_MEM {
96 &self.h_mem[n]
97 }
98 #[doc = "Iterator for array of:"]
99 #[doc = "0x60..0x70 - The memory that stores GCM hash subkey"]
100 #[inline(always)]
101 pub fn h_mem_iter(&self) -> impl Iterator<Item = &H_MEM> {
102 self.h_mem.iter()
103 }
104 #[doc = "0x70..0x80 - The memory that stores J0"]
105 #[inline(always)]
106 pub const fn j0_mem(&self, n: usize) -> &J0_MEM {
107 &self.j0_mem[n]
108 }
109 #[doc = "Iterator for array of:"]
110 #[doc = "0x70..0x80 - The memory that stores J0"]
111 #[inline(always)]
112 pub fn j0_mem_iter(&self) -> impl Iterator<Item = &J0_MEM> {
113 self.j0_mem.iter()
114 }
115 #[doc = "0x80..0x90 - The memory that stores T0"]
116 #[inline(always)]
117 pub const fn t0_mem(&self, n: usize) -> &T0_MEM {
118 &self.t0_mem[n]
119 }
120 #[doc = "Iterator for array of:"]
121 #[doc = "0x80..0x90 - The memory that stores T0"]
122 #[inline(always)]
123 pub fn t0_mem_iter(&self) -> impl Iterator<Item = &T0_MEM> {
124 self.t0_mem.iter()
125 }
126 #[doc = "0x90 - DMA-AES working mode register"]
127 #[inline(always)]
128 pub const fn dma_enable(&self) -> &DMA_ENABLE {
129 &self.dma_enable
130 }
131 #[doc = "0x94 - AES cipher block mode register"]
132 #[inline(always)]
133 pub const fn block_mode(&self) -> &BLOCK_MODE {
134 &self.block_mode
135 }
136 #[doc = "0x98 - AES block number register"]
137 #[inline(always)]
138 pub const fn block_num(&self) -> &BLOCK_NUM {
139 &self.block_num
140 }
141 #[doc = "0x9c - Standard incrementing function configure register"]
142 #[inline(always)]
143 pub const fn inc_sel(&self) -> &INC_SEL {
144 &self.inc_sel
145 }
146 #[doc = "0xa0 - Additional Authential Data block number register"]
147 #[inline(always)]
148 pub const fn aad_block_num(&self) -> &AAD_BLOCK_NUM {
149 &self.aad_block_num
150 }
151 #[doc = "0xa4 - AES remainder bit number register"]
152 #[inline(always)]
153 pub const fn remainder_bit_num(&self) -> &REMAINDER_BIT_NUM {
154 &self.remainder_bit_num
155 }
156 #[doc = "0xa8 - AES continue register"]
157 #[inline(always)]
158 pub const fn continue_(&self) -> &CONTINUE {
159 &self.continue_
160 }
161 #[doc = "0xac - AES Interrupt clear register"]
162 #[inline(always)]
163 pub const fn int_clr(&self) -> &INT_CLR {
164 &self.int_clr
165 }
166 #[doc = "0xb0 - AES Interrupt enable register"]
167 #[inline(always)]
168 pub const fn int_ena(&self) -> &INT_ENA {
169 &self.int_ena
170 }
171 #[doc = "0xb4 - AES version control register"]
172 #[inline(always)]
173 pub const fn date(&self) -> &DATE {
174 &self.date
175 }
176 #[doc = "0xb8 - AES-DMA exit config"]
177 #[inline(always)]
178 pub const fn dma_exit(&self) -> &DMA_EXIT {
179 &self.dma_exit
180 }
181}
182#[doc = "KEY (rw) register accessor: Key material key_%s configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`key::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@key`] module"]
183pub type KEY = crate::Reg<key::KEY_SPEC>;
184#[doc = "Key material key_%s configure register"]
185pub mod key;
186#[doc = "TEXT_IN (rw) register accessor: source text material text_in_%s configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`text_in::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`text_in::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_in`] module"]
187pub type TEXT_IN = crate::Reg<text_in::TEXT_IN_SPEC>;
188#[doc = "source text material text_in_%s configure register"]
189pub mod text_in;
190#[doc = "TEXT_OUT (rw) register accessor: result text material text_out_%s configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`text_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`text_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@text_out`] module"]
191pub type TEXT_OUT = crate::Reg<text_out::TEXT_OUT_SPEC>;
192#[doc = "result text material text_out_%s configure register"]
193pub mod text_out;
194#[doc = "MODE (rw) register accessor: AES Mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`] module"]
195pub type MODE = crate::Reg<mode::MODE_SPEC>;
196#[doc = "AES Mode register"]
197pub mod mode;
198#[doc = "ENDIAN (rw) register accessor: AES Endian configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`endian::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`endian::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endian`] module"]
199pub type ENDIAN = crate::Reg<endian::ENDIAN_SPEC>;
200#[doc = "AES Endian configure register"]
201pub mod endian;
202#[doc = "TRIGGER (w) register accessor: AES trigger register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigger::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigger`] module"]
203pub type TRIGGER = crate::Reg<trigger::TRIGGER_SPEC>;
204#[doc = "AES trigger register"]
205pub mod trigger;
206#[doc = "STATE (r) register accessor: AES state register\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"]
207pub type STATE = crate::Reg<state::STATE_SPEC>;
208#[doc = "AES state register"]
209pub mod state;
210#[doc = "IV_MEM (rw) register accessor: The memory that stores initialization vector\n\nYou can [`read`](crate::Reg::read) this register and get [`iv_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iv_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iv_mem`] module"]
211pub type IV_MEM = crate::Reg<iv_mem::IV_MEM_SPEC>;
212#[doc = "The memory that stores initialization vector"]
213pub mod iv_mem;
214#[doc = "H_MEM (rw) register accessor: The memory that stores GCM hash subkey\n\nYou can [`read`](crate::Reg::read) this register and get [`h_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`h_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@h_mem`] module"]
215pub type H_MEM = crate::Reg<h_mem::H_MEM_SPEC>;
216#[doc = "The memory that stores GCM hash subkey"]
217pub mod h_mem;
218#[doc = "J0_MEM (rw) register accessor: The memory that stores J0\n\nYou can [`read`](crate::Reg::read) this register and get [`j0_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`j0_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@j0_mem`] module"]
219pub type J0_MEM = crate::Reg<j0_mem::J0_MEM_SPEC>;
220#[doc = "The memory that stores J0"]
221pub mod j0_mem;
222#[doc = "T0_MEM (rw) register accessor: The memory that stores T0\n\nYou can [`read`](crate::Reg::read) this register and get [`t0_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`t0_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t0_mem`] module"]
223pub type T0_MEM = crate::Reg<t0_mem::T0_MEM_SPEC>;
224#[doc = "The memory that stores T0"]
225pub mod t0_mem;
226#[doc = "DMA_ENABLE (rw) register accessor: DMA-AES working mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_enable`] module"]
227pub type DMA_ENABLE = crate::Reg<dma_enable::DMA_ENABLE_SPEC>;
228#[doc = "DMA-AES working mode register"]
229pub mod dma_enable;
230#[doc = "BLOCK_MODE (rw) register accessor: AES cipher block mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`block_mode::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`block_mode::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@block_mode`] module"]
231pub type BLOCK_MODE = crate::Reg<block_mode::BLOCK_MODE_SPEC>;
232#[doc = "AES cipher block mode register"]
233pub mod block_mode;
234#[doc = "BLOCK_NUM (rw) register accessor: AES block number register\n\nYou can [`read`](crate::Reg::read) this register and get [`block_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`block_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@block_num`] module"]
235pub type BLOCK_NUM = crate::Reg<block_num::BLOCK_NUM_SPEC>;
236#[doc = "AES block number register"]
237pub mod block_num;
238#[doc = "INC_SEL (rw) register accessor: Standard incrementing function configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`inc_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inc_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inc_sel`] module"]
239pub type INC_SEL = crate::Reg<inc_sel::INC_SEL_SPEC>;
240#[doc = "Standard incrementing function configure register"]
241pub mod inc_sel;
242#[doc = "AAD_BLOCK_NUM (rw) register accessor: Additional Authential Data block number register\n\nYou can [`read`](crate::Reg::read) this register and get [`aad_block_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aad_block_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aad_block_num`] module"]
243pub type AAD_BLOCK_NUM = crate::Reg<aad_block_num::AAD_BLOCK_NUM_SPEC>;
244#[doc = "Additional Authential Data block number register"]
245pub mod aad_block_num;
246#[doc = "REMAINDER_BIT_NUM (rw) register accessor: AES remainder bit number register\n\nYou can [`read`](crate::Reg::read) this register and get [`remainder_bit_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`remainder_bit_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@remainder_bit_num`] module"]
247pub type REMAINDER_BIT_NUM = crate::Reg<remainder_bit_num::REMAINDER_BIT_NUM_SPEC>;
248#[doc = "AES remainder bit number register"]
249pub mod remainder_bit_num;
250#[doc = "CONTINUE (w) register accessor: AES continue register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`continue_::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@continue_`] module"]
251pub type CONTINUE = crate::Reg<continue_::CONTINUE_SPEC>;
252#[doc = "AES continue register"]
253pub mod continue_;
254#[doc = "INT_CLR (w) register accessor: AES Interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
255pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
256#[doc = "AES Interrupt clear register"]
257pub mod int_clr;
258#[doc = "INT_ENA (rw) register accessor: AES Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
259pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
260#[doc = "AES Interrupt enable register"]
261pub mod int_ena;
262#[doc = "DATE (rw) register accessor: AES version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
263pub type DATE = crate::Reg<date::DATE_SPEC>;
264#[doc = "AES version control register"]
265pub mod date;
266#[doc = "DMA_EXIT (w) register accessor: AES-DMA exit config\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_exit::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_exit`] module"]
267pub type DMA_EXIT = crate::Reg<dma_exit::DMA_EXIT_SPEC>;
268#[doc = "AES-DMA exit config"]
269pub mod dma_exit;