1#[doc = "Register `DDR` reader"]
2pub type R = crate::R<DDR_SPEC>;
3#[doc = "Field `SPI_FMEM_DDR_EN` reader - 1: in DDR mode, 0 in SDR mode"]
4pub type SPI_FMEM_DDR_EN_R = crate::BitReader;
5#[doc = "Field `SPI_FMEM_VAR_DUMMY` reader - Set the bit to enable variable dummy cycle in spi DDR mode."]
6pub type SPI_FMEM_VAR_DUMMY_R = crate::BitReader;
7#[doc = "Field `SPI_FMEM_DDR_RDAT_SWP` reader - Set the bit to reorder rx data of the word in spi DDR mode."]
8pub type SPI_FMEM_DDR_RDAT_SWP_R = crate::BitReader;
9#[doc = "Field `SPI_FMEM_DDR_WDAT_SWP` reader - Set the bit to reorder tx data of the word in spi DDR mode."]
10pub type SPI_FMEM_DDR_WDAT_SWP_R = crate::BitReader;
11#[doc = "Field `SPI_FMEM_DDR_CMD_DIS` reader - the bit is used to disable dual edge in command phase when DDR mode."]
12pub type SPI_FMEM_DDR_CMD_DIS_R = crate::BitReader;
13#[doc = "Field `SPI_FMEM_OUTMINBYTELEN` reader - It is the minimum output data length in the panda device."]
14pub type SPI_FMEM_OUTMINBYTELEN_R = crate::FieldReader;
15#[doc = "Field `SPI_FMEM_TX_DDR_MSK_EN` reader - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash."]
16pub type SPI_FMEM_TX_DDR_MSK_EN_R = crate::BitReader;
17#[doc = "Field `SPI_FMEM_RX_DDR_MSK_EN` reader - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash."]
18pub type SPI_FMEM_RX_DDR_MSK_EN_R = crate::BitReader;
19#[doc = "Field `SPI_FMEM_USR_DDR_DQS_THD` reader - The delay number of data strobe which from memory based on SPI clock."]
20pub type SPI_FMEM_USR_DDR_DQS_THD_R = crate::FieldReader;
21#[doc = "Field `SPI_FMEM_DDR_DQS_LOOP` reader - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."]
22pub type SPI_FMEM_DDR_DQS_LOOP_R = crate::BitReader;
23#[doc = "Field `SPI_FMEM_CLK_DIFF_EN` reader - Set this bit to enable the differential SPI_CLK#."]
24pub type SPI_FMEM_CLK_DIFF_EN_R = crate::BitReader;
25#[doc = "Field `SPI_FMEM_DQS_CA_IN` reader - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
26pub type SPI_FMEM_DQS_CA_IN_R = crate::BitReader;
27#[doc = "Field `SPI_FMEM_HYPERBUS_DUMMY_2X` reader - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."]
28pub type SPI_FMEM_HYPERBUS_DUMMY_2X_R = crate::BitReader;
29#[doc = "Field `SPI_FMEM_CLK_DIFF_INV` reader - Set this bit to invert SPI_DIFF when accesses to flash. ."]
30pub type SPI_FMEM_CLK_DIFF_INV_R = crate::BitReader;
31#[doc = "Field `SPI_FMEM_OCTA_RAM_ADDR` reader - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
32pub type SPI_FMEM_OCTA_RAM_ADDR_R = crate::BitReader;
33#[doc = "Field `SPI_FMEM_HYPERBUS_CA` reader - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
34pub type SPI_FMEM_HYPERBUS_CA_R = crate::BitReader;
35impl R {
36 #[doc = "Bit 0 - 1: in DDR mode, 0 in SDR mode"]
37 #[inline(always)]
38 pub fn spi_fmem_ddr_en(&self) -> SPI_FMEM_DDR_EN_R {
39 SPI_FMEM_DDR_EN_R::new((self.bits & 1) != 0)
40 }
41 #[doc = "Bit 1 - Set the bit to enable variable dummy cycle in spi DDR mode."]
42 #[inline(always)]
43 pub fn spi_fmem_var_dummy(&self) -> SPI_FMEM_VAR_DUMMY_R {
44 SPI_FMEM_VAR_DUMMY_R::new(((self.bits >> 1) & 1) != 0)
45 }
46 #[doc = "Bit 2 - Set the bit to reorder rx data of the word in spi DDR mode."]
47 #[inline(always)]
48 pub fn spi_fmem_ddr_rdat_swp(&self) -> SPI_FMEM_DDR_RDAT_SWP_R {
49 SPI_FMEM_DDR_RDAT_SWP_R::new(((self.bits >> 2) & 1) != 0)
50 }
51 #[doc = "Bit 3 - Set the bit to reorder tx data of the word in spi DDR mode."]
52 #[inline(always)]
53 pub fn spi_fmem_ddr_wdat_swp(&self) -> SPI_FMEM_DDR_WDAT_SWP_R {
54 SPI_FMEM_DDR_WDAT_SWP_R::new(((self.bits >> 3) & 1) != 0)
55 }
56 #[doc = "Bit 4 - the bit is used to disable dual edge in command phase when DDR mode."]
57 #[inline(always)]
58 pub fn spi_fmem_ddr_cmd_dis(&self) -> SPI_FMEM_DDR_CMD_DIS_R {
59 SPI_FMEM_DDR_CMD_DIS_R::new(((self.bits >> 4) & 1) != 0)
60 }
61 #[doc = "Bits 5:11 - It is the minimum output data length in the panda device."]
62 #[inline(always)]
63 pub fn spi_fmem_outminbytelen(&self) -> SPI_FMEM_OUTMINBYTELEN_R {
64 SPI_FMEM_OUTMINBYTELEN_R::new(((self.bits >> 5) & 0x7f) as u8)
65 }
66 #[doc = "Bit 12 - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash."]
67 #[inline(always)]
68 pub fn spi_fmem_tx_ddr_msk_en(&self) -> SPI_FMEM_TX_DDR_MSK_EN_R {
69 SPI_FMEM_TX_DDR_MSK_EN_R::new(((self.bits >> 12) & 1) != 0)
70 }
71 #[doc = "Bit 13 - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash."]
72 #[inline(always)]
73 pub fn spi_fmem_rx_ddr_msk_en(&self) -> SPI_FMEM_RX_DDR_MSK_EN_R {
74 SPI_FMEM_RX_DDR_MSK_EN_R::new(((self.bits >> 13) & 1) != 0)
75 }
76 #[doc = "Bits 14:20 - The delay number of data strobe which from memory based on SPI clock."]
77 #[inline(always)]
78 pub fn spi_fmem_usr_ddr_dqs_thd(&self) -> SPI_FMEM_USR_DDR_DQS_THD_R {
79 SPI_FMEM_USR_DDR_DQS_THD_R::new(((self.bits >> 14) & 0x7f) as u8)
80 }
81 #[doc = "Bit 21 - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS."]
82 #[inline(always)]
83 pub fn spi_fmem_ddr_dqs_loop(&self) -> SPI_FMEM_DDR_DQS_LOOP_R {
84 SPI_FMEM_DDR_DQS_LOOP_R::new(((self.bits >> 21) & 1) != 0)
85 }
86 #[doc = "Bit 24 - Set this bit to enable the differential SPI_CLK#."]
87 #[inline(always)]
88 pub fn spi_fmem_clk_diff_en(&self) -> SPI_FMEM_CLK_DIFF_EN_R {
89 SPI_FMEM_CLK_DIFF_EN_R::new(((self.bits >> 24) & 1) != 0)
90 }
91 #[doc = "Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR."]
92 #[inline(always)]
93 pub fn spi_fmem_dqs_ca_in(&self) -> SPI_FMEM_DQS_CA_IN_R {
94 SPI_FMEM_DQS_CA_IN_R::new(((self.bits >> 26) & 1) != 0)
95 }
96 #[doc = "Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram."]
97 #[inline(always)]
98 pub fn spi_fmem_hyperbus_dummy_2x(&self) -> SPI_FMEM_HYPERBUS_DUMMY_2X_R {
99 SPI_FMEM_HYPERBUS_DUMMY_2X_R::new(((self.bits >> 27) & 1) != 0)
100 }
101 #[doc = "Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. ."]
102 #[inline(always)]
103 pub fn spi_fmem_clk_diff_inv(&self) -> SPI_FMEM_CLK_DIFF_INV_R {
104 SPI_FMEM_CLK_DIFF_INV_R::new(((self.bits >> 28) & 1) != 0)
105 }
106 #[doc = "Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[25:4\\], 6'd0, spi_usr_addr_value\\[3:1\\], 1'b0}."]
107 #[inline(always)]
108 pub fn spi_fmem_octa_ram_addr(&self) -> SPI_FMEM_OCTA_RAM_ADDR_R {
109 SPI_FMEM_OCTA_RAM_ADDR_R::new(((self.bits >> 29) & 1) != 0)
110 }
111 #[doc = "Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT\\[31:0\\] = {spi_usr_addr_value\\[19:4\\], 13'd0, spi_usr_addr_value\\[3:1\\]}."]
112 #[inline(always)]
113 pub fn spi_fmem_hyperbus_ca(&self) -> SPI_FMEM_HYPERBUS_CA_R {
114 SPI_FMEM_HYPERBUS_CA_R::new(((self.bits >> 30) & 1) != 0)
115 }
116}
117#[cfg(feature = "impl-register-debug")]
118impl core::fmt::Debug for R {
119 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
120 f.debug_struct("DDR")
121 .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
122 .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
123 .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
124 .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
125 .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
126 .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
127 .field("spi_fmem_tx_ddr_msk_en", &self.spi_fmem_tx_ddr_msk_en())
128 .field("spi_fmem_rx_ddr_msk_en", &self.spi_fmem_rx_ddr_msk_en())
129 .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
130 .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
131 .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
132 .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
133 .field(
134 "spi_fmem_hyperbus_dummy_2x",
135 &self.spi_fmem_hyperbus_dummy_2x(),
136 )
137 .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
138 .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
139 .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
140 .finish()
141 }
142}
143#[doc = "SPI0 flash DDR mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
144pub struct DDR_SPEC;
145impl crate::RegisterSpec for DDR_SPEC {
146 type Ux = u32;
147}
148#[doc = "`read()` method returns [`ddr::R`](R) reader structure"]
149impl crate::Readable for DDR_SPEC {}
150#[doc = "`reset()` method sets DDR to value 0x3020"]
151impl crate::Resettable for DDR_SPEC {
152 const RESET_VALUE: u32 = 0x3020;
153}